REV. A

–10–

AD7834/AD7835

Table IV. Code Table for Unipolar Operation

Binary Number in DAC Latch

Analog Output

MSB

LSB

11

1111

1111

1111

10

0000

0000

0000

01

1111

1111

1111

00

0000

0000

0001

00

0000

0000

0000

0 V

NOTE

µV.

Bipolar Configuration

Figure 14 shows the AD7834/AD7835 set up for

±5 V opera-

tion. The AD588 provides precision

±5 V tracking outputs

AD7835. The code table for bipolar operation of the AD7834/

AD7835 is shown in Table V.

+15V

+5V

(–5 TO +5V)

6

3

4

C1

1µF

AGND

DGND

–15V

R2

100k

Ω

AD7834/

AD7835

*

SIGNAL

GND

2

14

15

16

12

8

13

11

10

5

9

7

R3

100k

Ω

R1

39k

Ω

1

AD588

Figure 14. Bipolar

±5 V Operation

Table V. Code Table for Bipolar Operation

Binary Number in DAC Latch Analog Output

MSB

LSB

11

1111

1111

1111

10

0000

0000

0001

10

0000

0000

0000

01

1111

1111

1111

00

0000

0000

0001

00

0000

0000

0000

NOTE

610

µV.

In Figure 14, full-scale and bipolar zero adjustments are pro-

vided by varying the gain and balance on the AD588. R2 varies

the gain on the AD588 while R3 adjusts the offset of both the

+5 V and –5 V outputs together with respect to ground.

For bipolar-zero adjustment, the DAC is loaded with

is adjusted by loading the DAC with all 1s and adjusting R2 un-

When bipolar-zero and full-scale adjustment are not needed, R2

and R3 can be omitted. Pin 12 on the AD588 should be con-

nected to Pin 11 and Pin 5 should be left floating.

When 14-bit transfers are being used, the DAC output voltages,

input registers in one of two ways. The first method normally

keeps LDAC high and only pulses LDAC low momentarily to

update all DAC latches simultaneously with the contents of

their respective input registers. The second method ties LDAC

low and channel updating occurs on a per channel basis after

new data is loaded to an input register.

In order to avoid the DAC output going to an intermediate

value during a 2-byte transfer, LDAC should not be tied low

permanently, but should be held high until the 2 bytes are writ-

ten to the input register. When the selected input register has

been loaded with the 2 bytes, LDAC should then be pulsed low

to update the DAC latch and, hence, perform the digital-to-

analog conversion.

In many applications, it may be acceptable to allow the DAC

output to go to an intermediate value during a 2-byte transfer.

In such applications, LDAC can be tied low, thus using one less

control line.

The actual DAC input register that is being written to is deter-

mined by the logic levels present on the devices address lines, as

shown in Table III.

Table III. AD7835—Address Line Truth Table

A2

A1

A0

DAC Selected

0

0

0

DAC 1

0

0

1

DAC 2

0

1

0

DAC 3

0

1

1

DAC 4

1

X

X

All DACs Selected

Unipolar Configuration

Figure 13 shows the AD7834/AD7835 in the unipolar binary

Table IV gives the code table for unipolar operation of the

AD7834/AD7835.

+15V

+5V

(0 TO +5V)

2

6

8

5

4

SIGNAL

GND

C1

1nF

AGND

DGND

–15V

R1

10k

Ω

AD7834/

AD7835

*

AD586

SIGNAL

GND

Figure 13. Unipolar +5 V Operation

Offset and gain may be adjusted in Figure 13 as follows: To ad-

gain adjustment, the AD7834/AD7835 should be loaded with

4.999695.

Many circuits will not require these offset and gain adjustments. In

these circuits R1 can be omitted. Pin 5 of the AD586 may be left

0 V.