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AD7884 Datasheet(PDF) 6 Page - Analog Devices |
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AD7884 Datasheet(HTML) 6 Page - Analog Devices |
6 / 16 page AD7884/AD7885 REV. C –6– PIN FUNCTION DESCRIPTION AD7884 AD7885 AD7885A Description VINV VINV VINV This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows the inversion of the supplied +3 V reference. VREF– VREF– VREF– This is the negative reference input, and it can be obtained by using an external amplifier to invert the positive reference input. In this case, the amplifier output is connected to VREF–. See Figure 6. ±3 V INS_ ±3 V INS This is the analog input sense pin for the ±3 volt analog input range on the AD7884 and AD7885A. ±3 V INF_ ±3 V INF This is the analog input force pin for the ±3 volt analog input range on the AD7884 and AD7885A. When using this input range, the ±5 V INF and ± 5 VINS pins should be tied to AGND. – ±3 V IN – This is the analog input pin for the ±3 volt analog input range on the AD7885. When us- ing this input range, the ±5 V INF and ±5 V INS pins should be tied to AGND. ±5 V INS ±5 V INS ±5 V INS This is the analog input sense pin for the ±5 volt analog input range on both the AD7884, AD7885 and AD7885A. ±5 V INF ±5 V INF ±5 V INF This is the analog input force pin for the ±5 volt analog input range on both the AD7884, AD7885 and AD7885A. When using this input range, the ±3 V INF and ±3 V INS pins should be tied to AGND. AGNDS AGNDS AGNDS This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier. AGNDF AGNDF AGNDF This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier. AVDD AVDD AVDD Positive analog power rail for the sample-and-hold amplifier and the residue amplifier. AVSS AVSS AVSS Negative analog power rail for the sample-and-hold amplifier and the residue amplifier. GND GND GND This is the ground return for sample-and-hold section. VSS VSS VSS Negative supply for the 9-bit ADC. VDD VDD VDD Positive supply for the 9-bit ADC and all device logic. CONVST CONVST CONVST This asynchronous control input starts conversion. CS CS CS Chip Select control input. RD RD RD Read control input. This is used in conjunction with CS to read the conversion result from the device output latch. – HBEN HBEN High Byte Enable. Active high control input for the AD7885. It selects either the high or the low byte of the conversion for reading. BUSY BUSY BUSY Busy output. The Busy output goes low when conversion begins and stays low until it is completed, at which time it goes high. DB0–DB15 – – Sixteen-bit parallel data word output on the AD7884. – DB0–DB7 DB0–DB7 Eight-bit parallel data byte output on the AD7885. DGND DGND DGND Ground return for all device logic. VREF+FVREF+FVREF+F Reference force input. VREF+SVREF+SVREF+S Reference sense input. The device operates from a +3 V reference. |
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