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AD808-622BR Datasheet(PDF) 9 Page - Analog Devices |
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AD808-622BR Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page AD808 REV. 0 –9– USING THE AD808 Acquisition Time This is the transient time, measured in bit periods, that required for the AD808 to lock onto the input data from its free running state. Ground Planes The use of one ground plane for connections to both analog and digital grounds is recommended. Power Supply Connections The use of a 10 µF capacitor between V CC and ground is recom- mended. The +5 V power supply connection to VCC2 should be carefully isolated. The VCC2 pin is used inside the AD808 to provide the CLKOUT and DATAOUT signals. Use a 0.1 µF decoupling capacitor between IC power supply input and ground. This decoupling capacitor should be posi- tioned as closed to the IC as possible. Refer to the schematic in Figure 15 for advised connections. Transmission Lines Use 50 Ω transmission line for PIN, NIN, CLKOUT, and DATAOUT signals. Terminations Use metal, thick-film, 1% termination resistors for PIN, NIN, CLKOUT, and DATAOUT signals. These termination resistors must be positioned as close to the IC as possible. Use individual connections, not daisy chained, for connections from the +5 V to load resistors for PIN, NIN, CLKOUT, and DATAOUT signals. Loop Damping Capacitor, CD A ceramic capacitor may be used for the loop damping capaci- tor. Using a 0.47 µF, ± 20% capacitor provides < 0.1 dB jitter peaking. AD808 Output Squelch Circuit A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and data outputs when SDOUT indicates a loss of signal (Figure 16). The VCC2 supply pin draws roughly 72 mA (14 mA for each of 4 ECL loads, plus 16 mA for all 4 ECL output stages). This means that selection of a FET with ON RESISTANCE of 0.5 Ω will affect the common mode of the ECL outputs by only 36 mV. 1 2 5 6 7 3 4 8 16 15 12 11 10 14 13 9 VEE SDOUT AVCC2 PIN NIN AVCC1 THRADJ AVEE DATAOUTN DATAOUTP CLKOUTN CLKOUTP VCC1 CF1 CF2 VCC2 AD808 TO VCC1, AVCC, AVCC2 P_FET BYPASS CAP 5V Figure 16. Squelch Circuit Schematic |
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