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GRM185B31A105KE35 Datasheet(PDF) 7 Page - Panasonic Semiconductor |
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GRM185B31A105KE35 Datasheet(HTML) 7 Page - Panasonic Semiconductor |
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7 / 48 page  7 AN30183A Ver. AEB *2 kHz 400 — 0 — FOSC SCL clock frequency *2 μA 10 — –10 SCL, SDA = 0.1 × V DVDDmax to 0.9 × V DVDDmax IL Input current each I/O pin *2 V 0.2 × VDVDD — 0 VDVDD < 2 V SDA(sink current) = 3 mA VOL2 Low-level output voltage 2 *2 V 0.4 — 0 VDVDD > 2 V SDA(sink current) = 3 mA VOL1 Low-level output voltage 1 I2C Bus (Internal I/O Stage Characteristics) *1 *2 V VDVDD max + 0.5 — 0.7 × VDVDD Voltage which recognized that SDA and SCL are High-level VIH1 High-level input voltage *1 *2 V 0.3 × VDVDD — –0.5 Voltage which recognized that SDA and SCL are Low-level VIL1 Low-level input voltage Reference values Typ Unit Max Notes Min Conditions Symbol Parameter APPLICATION INFORMATION REFERENCE VALUES FOR DESIGN VVBAT(DDVBAT1 = VB = VIN2) = 3.7V, DVDD = 1.85V Ta = 25 °C ± 2 °C unless otherwise noted. Notes) *1 : The input threshold voltage of I2C bus (Vth) is linked to V DVDD. In case the pull-up voltage is not V DVDD, the threshold voltage (Vth) is fixed to ((VDVDD / 2) ± (Schmitt width) / 2 ) and High-level, Low-level of input voltage are not specified. In this case, pay attention to Low-level (max.) value (V ILmax). It is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (V DVDD). *2 :Checked by design, not production tested. |
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