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GRM21BB31A475KA74 Datasheet(PDF) 11 Page - Panasonic Semiconductor |
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GRM21BB31A475KA74 Datasheet(HTML) 11 Page - Panasonic Semiconductor |
11 / 48 page 11 AN30183A Ver. AEB *2 μA 17 8 — DDVBAT1 = VB = VIN2 = 3.7 V DCDC1, LDO1 to 4 = OFF RESET= “H” IBAT_4 Static consumption current 2 Consumption current *2 *3 V — — 0.1 × VDVDD — VnL Noise margin at the Low-level for each connected device I2C bus (Bus line specifications) (continued) *2 *3 V — — 0.2 × VDVDD — VnH Noise margin at the High-level for each connected device *2 *3 pF 400 — — — Cb Capacitive load for each bus line Reference values Typ Unit Max Notes Min Conditions Symbol Parameter Notes) *2 :Checked by design, not production tested. *3 :The timing of Fast-mode devices in I2C-bus is specified as the following. All values referred to V IHmin and VILmax level. S : START condition Sr : Repeat START condition P : STOP condition SCL SDA tLOW tf tr tHD;STA tHD;DAT tHIGH tSU;DAT tf tSU;STA tHD;STA tSP Sr tSU;STO tBUF PS tr S APPLICATION INFORMATION (Continued) REFERENCE VALUES FOR DESIGN VVBAT(DDVBAT1 = VB = VIN2) = 3.1V to 4.5V, DVDD = 1.85V , DC-DC : Co = 4.7 µF, Lo = 1 µH / LDO : Co =1.0 µF Ta = 25 °C ± 2 °C unless otherwise noted. Notes) *2 :Checked by design, not production tested. |
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