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AD842SQ Datasheet(PDF) 7 Page - Analog Devices |
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AD842SQ Datasheet(HTML) 7 Page - Analog Devices |
7 / 10 page AD842 –7– REV. E OFFSET NULLING The input offset voltage of the AD842 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in Figure 21 can be used. AD842 SETTLING TIME Figures 22 and 24 show the settling performance of the AD842 in the test circuit shown in Figure 23. Settling time is defined as: The interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. This definition encompasses the major components which com- prise settling time. They include (1) propagation delay through the amplifier; (2) slewing time to approach the final output value; (3) the time of recovery from the overload associated with slew- ing and (4) linear settling to within the specified error band. Expressed in these terms, the measurement of settling time is obviously a challenge and needs to be done accurately to assure the user that the amplifier is worth consideration for the application. – + AD842 RL 2.2 F 0.1 F –VS OUTPUT 2.2 F 0.1 F +VS 10k INPUT Figure 21. Offset Nulling (DIP Pinout) Figure 22. 0.01% Settling Time 2.2 F 0.1 F AD842 499 499 2.2 F 0.1 F –15V DDD5109 FLAT-TOP PULSE GENERATOR 50 499 1k 499 1k +15V HP6263 ERROR AMP ( 15) TEK 7603 OSCILLOSCOPE TEK 7A13 TEK 7A16 FET PROBE TEK P6201 Figure 23. Settling Time Test Circuit Figure 23 shows how measurement of the AD842’s 0.01% set- tling in 100 ns was accomplished by amplifying the error signal from a false summing junction with a very high-speed propri- etary hybrid error amplifier specially designed to enable testing of small settling errors. The device under test was driving a 300 Ω load. The input to the error amp is clamped in order to avoid possible problems associated with the overdrive recovery of the oscilloscope input amplifier. The error amp gains the error from the false summing junction by 15, and it contains a gain vernier to fine trim the gain. Figure 24 shows the “long term” stability of the settling charac- teristics of the AD842 output after a 10 V step. There is no evidence of settling tails after the initial transient recovery time. The use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of tran- sistor isolation capacitance discharge and thermally induced shifts in circuit operating points. These problems do not occur even under high output current conditions. |
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