© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FPF1013 / FPF1014 • Rev. 1.0.9

10

Physical Dimensions

Figure 24. 6- Ball Wafer-Level Chip-Scale Package (WLCSP) 2X3 ARRAY, 0.5 mm Pitch, 300 µm Ball

E

D

X

Y

950 µm ±30 µm

1450 µm ±30 µm

225 µm

225 µm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

BOTTOM VIEW

SIDE VIEWS

RECOMMENDED LAND PATTERN

BALL A1

INDEX AREA

SEATING PLANE

A1

F

(NSMD PAD TYPE)

(Ø0.350)

SOLDER MASK

OPENING

(X) ±0.018

(Y) ±0.018

(Ø0.250)

Cu Pad

0.06 C

0.05 C

E

D

F

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 1994.

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS

±43 MICRONS (539-625 MICRONS).

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

G. DRAWING FILNAME: MKT-UC006AFrev2.

0.03 C

2X

0.03 C

2X

Ø0.315 +/- .025

6X

1 2

A

B

C

0.332±0.018

0.250±0.025

D

E

(1.00)

(0.50)

0.005

CA B

0.50

0.50

1.00

0.625

0.539

TOP VIEW

B

A

C