© 2011 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FPF1203 / FPF1203L / FPF1204 / FPF12045 • Rev. 1.2.0

11

Physical Dimensions

Figure 24. 4-Bump, 0.76 x 0.76 mm, Wafer-Level Chip-Scale Packaging

Product Dimensions

D

E

X

Y

760 µm ± 30 µm

760 µm ± 30 µm

0.180 mm± 0.018 µm

0.180 mm± 0.018 µm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

BOTTOM VIEW

SIDE VIEWS

TOP VIEW

RECOMMENDED LAND PATTERN

BALL A1

INDEX AREA

A1

0.005

CA B

F

(NSMD PAD TYPE)

B

A

0.292±0.018

0.208±0.021

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASME Y14.5M, 1994.

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E. PACKAGE NOMINAL HEIGHT IS 500 MICRONS

±39 MICRONS (461-539 MICRONS).

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

G. DRAWING FILNAME: MKT-UC004AFrev1.

0.03 C

2X

0.03 C

2X

1 2

A

B

0.40

0.40

(X)±0.018

SEATING PLANE

C

0.06 C

0.05 C

E

D

D

E

0.40

0.40

Ø0.20

Cu Pad

Ø0.30

Solder Mask

(Y)±0.018

Ø0.260±0.020

4X

0.539

0.461

F