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AD876JR-8 Datasheet(PDF) 11 Page - Analog Devices |
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AD876JR-8 Datasheet(HTML) 11 Page - Analog Devices |
11 / 16 page AD876 REV. B –11– For DRVDD = 5 V, the AD876 output signal swing is compat- ible with both high speed CMOS and TTL logic families. For TTL, the AD876 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD876 sustains 20 MSPS operation with DRVDD = 3.3 V. In all cases, check your logic family data sheets for compatibility with the AD876 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD876 can be placed in a high im- pedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. Note that this function is not intended for enabling/ disabling the ADC outputs from a bus at 20 MSPS. Also, to avoid corruption of the sampled analog signal during conversion (3.5 clock cycles), it is highly recommended that the AD876 outputs be enabled on the bus prior to the first sampling. For the purpose of budgetary timing, the maximum access and float delay times (tDD, tHL shown in Figure 15) for the AD876 are 150 ns. THREE-STATE ACTIVE HIGH IMPEDANCE D0–D9 tDD tHL Figure 22. High-Impedance Output Timing Diagram Table I. Output Data Format Approx. THREE- DATA AIN (V) STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 >4 0 1111111111 4 0 1111111111 3 0 1000000000 2 0 0000000000 <2 0 0000000000 X 1 ZZZZZZZZZZ A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD876 will drop below 50 mW. GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD876 have been separated to optimize the management of return currents in a system. It is recommended that a printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes be used with the AD876. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electro- magnetic interference (EMI) and an overall improvement in performance. It is important to design a layout which prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD876. A solid ground plane under the AD876 is also acceptable if the power and ground return currents are managed carefully. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. For further layout suggestions, see the AD876 Evaluation Board data sheet. DIGITAL OUTPUTS Each of the on-chip buffers for the AD876 output bits (D0–D9) is powered from the DRVDD supply pins, separate from AVDD or DVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy gener- ated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. |
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