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AD9501 Datasheet(PDF) 6 Page - Analog Devices |
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AD9501 Datasheet(HTML) 6 Page - Analog Devices |
6 / 12 page AD9501 REV. A –6– Offset between the two levels is necessary for three reasons. First, offset allows the ramp to reset and settle without re- entering the voltage range of the DAC. Second, the DAC may overshoot as it switches to its most positive value (00H); this could lead to false output pulses if there were no offset between the ramp reset voltage and the upper reference. Overshoot on the ramp could also lead to false outputs without the offset. Finally, the ramp is slightly nonlinear for a short interval when it is first started; the offset shifts the most positive DAC level below this nonlinear region and maintains ramp linearity for short programmed delay settings. Pin 8 of the AD9501 is called OFFSET ADJUST (see block diagram) and allows the user to control the amount of offset separating the initial ramp voltage and the most positive DAC reference. This, in turn, causes the Ramp Generator delay to vary. Figure 2 shows differences in timing which occur if OFFSET ADJUST Pin 8 is grounded or open. The variable Ramp Generator delay is the major component of the three components which comprise Minimum Delay (tPD) and, therefore, is affected by the connection to Pin 8. It is preferable to ground Pin 8 because the smaller offset that results from leaving it open increases the possibility of false out- put pulses. When grounding the pin, it should be grounded directly or connected to ground through a resistor or potentiom- eter with a value of 10 k Ω or less. Caution is urged when using resistance in series with Pin 8. The possibility of false output pulses, as discussed above, is in- creased under these circumstances. Using resistance in series with Pin 8 is recommended only when matching minimum de- lays between two or more AD9501 devices; it is not recom- mended if using a single AD9501. Changing the resistance between Pin 8 and ground from zero to 10 k Ω varies the Ramp Generator Delay by approximately 35%. The Full-Scale Delay Range (tDFS) can be calculated from the equation: (tDFS ) = RSET ×(CEXT + 8.5 pF ) × 3.84 Whenever Full-Scale Delay Range is 326 ns or less, CEXT should be left open. Additional capacitance and/or larger values of RSET increase the Linear Ramp Settling Time, which reduces the maximum trigger rate. When delays longer than 326 ns are required, up to 500 pF can be connected from CEXT to +VS. RSET should be selected in the range from 50 Ω to 10 kΩ. Graph 1 shows typical Full-Scale Delay Ranges for various values of RSET and CEXT. Figure 2. AD9501 Minimum Delay (tPD) vs. Full-Scale Delay Range (tDFS) |
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