AD9696/AD9698

–4–

REV. B

PIN CONFIGURATIONS

AD9696KN/KR/KQ/TQ/TZ

TOP VIEW

(Not to Scale)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

AD9698KN/KQ/TQ

[AD9698KR/TZ PINOUTS SHOWN IN ( )]

LATCH

ENABLE

1

2

3

4

TOP VIEW

(Not to Scale)

5

6

7

8

+IN

–IN

GROUND

Name

Function

GROUND

Analog and digital ground return. All GROUND pins should be connected together and to a low impedance

ground plane near the comparator.

LATCH

ENABLE 1

block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)

N/C

No internal connection to comparator.

Negative power supply connection; nominally –5.2 V.

Inverting input of differential input stage for Comparator #1.

Noninverting input of differential input stage for Comparator #1.

Noninverting input of differential input stage for Comparator #2.

Inverting input of differential input stage for Comparator #2.

Positive power supply connection; nominally +5 V.

LATCH

ENABLE 2

block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-

age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.