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AD9752 Datasheet(PDF) 11 Page - Analog Devices |
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AD9752 Datasheet(HTML) 11 Page - Analog Devices |
11 / 23 page REV. 0 AD9752 –11– The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and IREF is varied by an external voltage, VGC, applied to RSET via an ampli- fier. An example of this method is shown in Figure 21, in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 V. The external voltage, VGC, is referenced to ACOM and should not exceed 1.2 V. The value of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA and 625 µA, respectively. The associated equations in Figure 21 can be used to determine the value of RSET. 150pF +1.2V REF AVDD REFLO CURRENT SOURCE ARRAY AVDD REFIO FS ADJ RSET AD9752 IREF VGC 1 F IREF = (1.2–VGC)/RSET WITH VGC < VREFIO AND 62.5 A IREF 625A Figure 21. Dual-Supply Gain Control Circuit ANALOG OUTPUTS The AD9752 produces two complementary current outputs, IOUTA and IOUTB, which may be configured for single-end or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Figure 22 shows the equivalent analog output circuit of the AD9752 consisting of a parallel combination of PMOS differen- tial current switches associated with each segmented current source. The output impedance of IOUTA and IOUTB is deter- mined by the equivalent parallel combination of the PMOS switches and is typically 100 k Ω in parallel with 5 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) and, to a lesser extent, the analog supply voltage, AVDD, and full-scale current, IOUTFS. Although the output impedance’s signal dependency can be a source of dc nonlinearity and ac linear- ity (i.e., distortion), its effects can be limited if certain precau- tions are noted. AVDD IOUTB IOUTA RLOAD RLOAD Figure 22. Equivalent Analog Output IOUTA and IOUTB also have a negative and positive voltage compliance range. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9752. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. Operation beyond the positive compliance range will induce clipping of the output signal which severely degrades the AD9752’s linearity and distortion performance. For applications requiring the optimum dc linearity, IOUTA and/or IOUTB should be maintained at a virtual ground via an I-V op amp configuration. Maintaining IOUTA and/or IOUTB at a virtual ground keeps the output impedance of the AD9752 fixed, significantly reducing its effect on linearity. However, it does not necessarily lead to the optimum distortion perfor- mance due to limitations of the I-V op amp. Note that the INL/DNL specifications for the AD9752 are measured in this manner using IOUTA. In addition, these dc linearity specifications remain virtually unaffected over the specified power supply range of 4.5 V to 5.5 V. Operating the AD9752 with reduced voltage output swings at IOUTA and IOUTB in a differential or single-ended output configuration reduces the signal dependency of its output impedance thus enhancing distortion performance. Although the voltage compliance range of IOUTA and IOUTB extends from –1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed approximately 0.5 V. A properly se- lected transformer with a grounded center-tap will allow the AD9752 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at IOUTA and IOUTB. DC-coupled applications requiring a differential or single-ended output configuration should size RLOAD accordingly. Refer to Applying the AD9752 section for examples of various output configurations. The most significant improvement in the AD9752’s distortion and noise performance is realized using a differential output configuration. The common-mode error sources of both IOUTA and IOUTB can be substantially reduced by the common-mode rejection of a transformer or differential am- plifier. These common-mode error sources include even- order distortion products and noise. The enhancement in distortion performance becomes more significant as the recon- structed waveform’s frequency content increases and/or its amplitude decreases. The distortion and noise performance of the AD9752 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, IOUTFS. Operating the analog supply at 5.0 V ensures maximum headroom for its internal PMOS current sources and differential switches leading to improved distortion performance. Although IOUTFS can be set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will provide the best dis- tortion and noise performance also shown in Figure 8. The noise performance of the AD9752 is affected by the digital sup- ply (DVDD), output frequency, and increases with increasing clock rate as shown in Figure 11. Operating the AD9752 with low voltage logic levels between 3 V and 3.3 V will slightly re- duce the amount of on-chip digital noise. |
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