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EDJ4204EFBG Datasheet(PDF) 7 Page - Elpida Memory

Part # EDJ4204EFBG
Description  Differential clock inputs
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDJ4204EFBG Datasheet(HTML) 7 Page - Elpida Memory

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EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Preliminary Data Sheet E1922E11 (Ver. 1.1)
7
1.3
Recommended DC Operating Conditions
Notes: 1.
Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very
long period of time (e.g. 1 sec).
2.
If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3.
Under these supply voltages, the device operates to this DDR3L specifcation.
4.
Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while
5.
VDD and VDDQ are changed for DDR3 operation shown as following timing wave form.
Notes: 1.
If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2.
Under 1.5V operation, this DDR3L device operates to the DDR3 specifcations under the same speedtimings as defined
for this device.
3.
Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ
are changed for DDR3L operation shown as below.
Table 3: Recommended DC Operating Conditions (TC = 0
°C to +85°C), DDR3L Operation
Parameter
Symbol
min.
typ.
max.
Unit
Notes
Supply voltage
VDD
1.283
1.35
1.45
V
1, 2, 3, 4
Supply voltage for DQ
VDDQ
1.283
1.35
1.45
V
1, 2, 3, 4
Table 4: Recommended DC Operating Conditions (TC = 0
°C to +85°C), DDR3 Operation
Parameter
Symbol
min
typ
max
Unit
Notes
Supply voltage
VDD
1.425
1.5
1.575
V
1, 2, 3
Supply voltage for DQ
VDDQ
1.425
1.5
1.575
V
1, 2, 3
Figure 1: VDD/VDDQ Voltage Switch between DDR3L and DDR3
T(min) = 10ns
T(min) = 200
µs
T(min) = 10ns
T = 500
µs
tIS
Note: 1. From time point Td until Tk, NOP or DES commands must be applied between MRS and ZQCL commands.
: VIH or VIL
CK, /CK
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
/RESET
CKE
Command
BA
ODT
RTT
tXPR
tMRD
tMRD
tMRD
tMOD
tCKSRX
tIS
tIS
tIS
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
T(min) = 10ns
tDLLK
tZQinit
*1
*1
Valid
Valid
Valid
Valid
MRS
Static low in case RTT_Nore is enabled at time Tg, otherwise static high or low
MRS
MRS
MRS
ZQCL
MR2
MR3
MR1
MR0


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