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EDJ4216BFBG-JS-F Datasheet(PDF) 3 Page - Elpida Memory |
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EDJ4216BFBG-JS-F Datasheet(HTML) 3 Page - Elpida Memory |
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3 / 32 page  EDJ4204BFBG, EDJ4208BFBG, EDJ4216BFBG Preliminary Data Sheet E1923E20 (Ver. 2.0) 3 Pin Configurations Pin Configurations ( ×4/×8 configuration) /xxx indicates active low signal. Notes: 1. Not internally connected with die. 2. Don't connect. Internally connected. 3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. Pin name Function Pin name Function A0 to A15*3 Address inputs A10(AP): Auto precharge A12(/BC): Burst chop /RESET*3 Active low asynchronous reset BA0 to BA2*3 Bank select VDD Supply voltage for internal circuit DQ0 to DQ7 Data input/output VSS Ground for internal circuit DQS, /DQS Differential data strobe VDDQ Supply voltage for DQ circuit TDQS, /TDQS Termination data strobe VSSQ Ground for DQ circuit /CS*3 Chip select VREFDQ Reference voltage for DQ /RAS, /CAS, /WE*3 Command input VREFCA Reference voltage for CA CKE*3 Clock enable ZQ Reference pin for ZQ calibration CK, /CK Differential clock input NC*1 No connection DM Write data mask NU*2 Not usable ODT*3 ODT control VSS VDD 1 VDDQ VSS VSS 2 VSSQ DQ0 VSS DQ2 NC VSSQ VDDQ VREFDQ VSS VDD /CS BA0 A7 /RESET NC A15 VDD 3 NC DQS /DQS NC /RAS /CAS /WE BA2 A9 A13 7 NC DM DQ1 VDD NC CK /CK A10(AP) NC A11 A14 8 VSS VSSQ VDDQ VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA A6 A8 CKE VSS VSS 9 VDD VSSQ VDDQ NC VDD (Top view) 78-ball FBGA (×4 configuration) ODT NC A B C D E F G H J A3 VDD A0 A12(/BC) BA1 VDD A5 VSS A2 A1 A4 VSS K L M N VSS VDD 1 VDDQ VSS VSS 2 VSSQ DQ0 VSS DQ2 DQ6 VSSQ VDDQ VREFDQ VSS VDD /CS BA0 A7 /RESET NC A15 VDD 3 NC DQS /DQS DQ4 /RAS /CAS /WE BA2 A9 A13 7 NU/(/TDQS) DM/TDQS DQ1 VDD DQ7 CK /CK A10(AP) NC A11 A14 8 VSS VSSQ VDDQ VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA A6 A8 CKE VSS VSS 9 VDD VSSQ VDDQ NC VDD (Top view) 78-ball FBGA (×8 configuration) ODT NC A B C D E F G H J A3 VDD A0 A12(/BC) BA1 VDD A5 VSS A2 A1 A4 VSS K L M N |
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