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AD9772 Datasheet(PDF) 7 Page - Analog Devices |
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AD9772 Datasheet(HTML) 7 Page - Analog Devices |
7 / 30 page REV. 0 AD9772 –7– PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1, 2, 19, 20 DCOM Digital Common. 3 DB13 Most Significant Data Bit (MSB). 4–15 DB12–DB1 Data Bits 1–12. 16 DB0 Least Significant Data Bit (LSB). 17 MOD0 Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High. 18 MOD1 Invokes “zero-stuffing” mode. Active High. Note, “quarter-wave” digital mixing occurs with MOD0 also set HIGH. 23, 24 NC No Connect, Leave Open. 21, 22, 47, 48 DVDD Digital Supply Voltage (+2.7 V to +3.6 V). 25 PLLLOCK Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is locked to input clock. Provides 1 × clock output when PLL clock multiplier is disabled. Maxi- mum fanout is one (i.e., <10 pF). 26 RESET Resets internal divider by bringing momentarily high when PLL is disabled to synchronize inter- nal 1 × clock to the input data and/or multiple AD9772 devices. 27, 28 DIV1, DIV0 DIV1 along with DIV0 sets the PLL’s prescaler divide ratio (refer to Table III.) 29 CLK+ Noniverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2). 30 CLK– Inverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2). 31 CLKCOM Clock Input Common. 32 CLKVDD Clock Input Supply Voltage (+2.7 V to +3.6 V). 33 PLLCOM Phase Lock Loop Common. 34 PLLVDD Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +3.6 V). To disable PLL clock multiplier, connect PLLVDD to PLLCOM. 35 LPF PLL Loop Filter Node. 36 SLEEP Power-Down Control Input. Active High. Connect to ACOM if not used. 37, 41, 44 ACOM Analog Common. 38 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 39 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. 40 FSADJ Full-Scale Current Output Adjust. 42 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 43 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 45, 46 AVDD Analog Supply Voltage (+2.7 V to +3.6 V). PIN CONFIGURATION 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) SLEEP LPF PLLVDD PLLCOM CLKVDD CLKCOM CLK– DCOM DCOM (MSB) DB13 DB12 DB11 DB10 DB9 NC = NO CONNECT DB8 DB7 DB6 DB5 CLK+ DIV0 DIV1 RESET AD9772 DB4 PLLLOCK |
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