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M12L64322A-6TG2U Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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M12L64322A-6TG2U Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
1 / 46 page ESMT M12L64322A (2U) Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2010 Revision: 1.0 1/46 SDRAM 512K x 32 Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 15.6μs refresh interval ORDERING INFORMATION Product ID Max Freq. Package Comments M12L64322A-5TG2U 200MHz 86 TSOPII Pb-free M12L64322A-6TG2U 166MHz 86 TSOPII Pb-free M12L64322A-7TG2U 143MHz 86 TSOPII Pb-free M12L64322A-5BG2U 200MHz 90 BGA Pb-free M12L64322A-6BG2U 166MHz 90 BGA Pb-free M12L64322A-7BG2U 143MHz 90 BGA Pb-free GENERAL DESCRIPTION The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATION (TOP VIEW) (TSOPII 86L, 400milX875mil Body, 0.5mm Pin Pitch) 1 2 3 4 5 6 7 8 9 VDD DQ 0 V DD Q DQ 1 DQ 2 V SS Q DQ 3 DQ 4 V DD Q 86 85 84 83 82 81 80 79 78 66 65 64 63 62 61 60 59 58 V SS DQ 1 5 V SSQ DQ 1 4 DQ 1 3 V DD Q DQ 1 2 DQ 1 1 V SSQ 10 11 12 13 14 15 16 17 18 19 20 DQ 5 DQ 6 V SS Q DQ 7 NC VDD DQ M0 WE CA S RA S CS 77 76 75 74 73 72 71 70 69 68 67 DQ 1 0 DQ 9 V DD Q DQ 8 NC V SS DQ M 1 NC NC CL K CK E NC DQ 3 1 V DD Q DQ 3 0 DQ 2 9 V SS Q DQ 2 8 DQ 2 7 V DD Q DQ 2 6 DQ 2 5 V SS Q DQ 2 4 V SS 21 22 23 24 25 26 27 28 29 NC BA0 BA1 A10/AP A0 A1 A2 DQM2 V DD 30 31 32 33 34 35 36 37 38 39 NC DQ 1 6 V SS Q DQ 1 7 DQ 1 8 V DD Q DQ 1 9 DQ 2 0 V SS Q DQ 2 1 DQ 2 2 40 41 42 43 V DD Q DQ2 3 V DD A9 A8 A7 A6 A5 A4 A3 DQ M 3 V SS 57 56 55 54 53 52 51 50 49 48 47 46 45 44 |
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