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AD9830AST Datasheet(PDF) 3 Page - Analog Devices |
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AD9830AST Datasheet(HTML) 3 Page - Analog Devices |
3 / 16 page AD9830 REV. A –3– TIMING CHARACTERISTICS Limit at TMIN to TMAX Parameter (A Version) Units Test Conditions/Comments t1 20 ns min MCLK Period t2 8 ns min MCLK High Duration t3 8 ns min MCLK Low Duration t4 1 8 ns min WR Rising Edge Before MCLK Rising Edge t4A 1 8 ns min WR Rising Edge After MCLK Rising Edge t5 8 ns min WR Pulse Width t6 t1 ns min Duration Between Consecutive WR Pulses t7 5 ns min Data/Address Setup Time t8 3 ns min Data/Address Hold Time t9 1 8 ns min FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge t9A 1 8 ns min FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge t10 t1 ns min RESET Pulse Duration NOTES 1See Pin Description section. Guaranteed by design, but not production tested. t1 t2 t3 t4A t4 t5 t6 MCLK WR Figure 2. WR–MCLK Relationship A0, A1, A2 DATA WR t6 t8 t7 t5 VALID DATA VALID DATA Figure 3. Writing to a Phase/Frequency Register t9 VALID DATA VALID DATA VALID DATA t9A t10 MCLK FSELECT PSEL0, PSEL1 RESET Figure 4. Control Timing (VDD = +5 V 5%; AGND = DGND = 0 V, unless otherwise noted) |
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