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M12L128168A-7TG2L Datasheet(PDF) 2 Page - Elite Semiconductor Memory Technology Inc. |
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M12L128168A-7TG2L Datasheet(HTML) 2 Page - Elite Semiconductor Memory Technology Inc. |
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2 / 45 page  ESMT M12L128168A (2L) Elite Semiconductor Memory Technology Inc. Publication Date: Jun. 2012 Revision: 1.3 2/45 BLOCK DIAGRAM PIN DESCRIPTION PIN NAME INPUT FUNCTION CLK System Clock Active on the positive going edge to sample all inputs CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK , CKE and L(U)DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby. A0 ~ A11 Address Row / column address are multiplexed on the same pins. Row address : RA0~RA11, column address : CA0~CA8 BA0 , BA1 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. (Enables row access & precharge.) CAS Column Address Strobe Latches column address on the positive going edge of the CLK with CAS low. (Enables column access.) WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins. VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic. VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. NC No Connection This pin is recommended to be left No Connection on the device. L(U)DQM DQ Mode Register Column Address Buffer & Counter Row Address Buffer & Refresh Counter Bank D Bank A Bank B Bank C Sense Amplifier Column Decoder Data Control Circuit Address Clock Generator CLK CKE CS RAS CAS WE |
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