ADG451/ADG452/ADG453

REV. A

–8–

FREQUENCY – Hz

1k

120

100

10k

100k

1M

10M

100

20

0

40

60

80

100M

Figure 9. Crosstalk vs. Frequency

200

100

10

–3.5

1

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

FREQUENCY – MHz

Figure 10. Frequency Response with Switch On

APPLICATION

Figure 11 illustrates a precise, fast, sample-and-hold circuit.

An AD845 is used as the input buffer while the output

operational amplifier is an AD711. During the track mode,

ADG451/

452/453

AD845

AD711

+15V

+5V

SW2

S

S

D

D

SW1

+15V

–15V

–15V

CH

2200pF

–15V

75

1000pF

+15V

2200pF

Figure 11. Fast, Accurate Sample-and-Hold Circuit

Due to switch and capacitor leakage, the voltage on the

hold capacitor will decrease with time. The ADG451/

ADG452/ADG453 minimizes this droop due to its low

leakage specifications. The droop rate is further minimized

by the use of a polystyrene hold capacitor. The droop rate

for the circuit shown is typically 30

µV/µs.

A second switch, SW2, that operates in parallel with SW1, is

included in this circuit to reduce pedestal error. Since both

switches will be at the same potential, they will have a differ-

ential effect on the op amp AD711, which will minimize

charge injection effects. Pedestal error is also reduced by the

work reduces the hold time glitch while optimizing the ac-

quisition time. Using the illustrated op amps and component

values, the pedestal error has a maximum value of 5 mV over

the

±10 V input range. Both the acquisition and settling

times are 850 ns.