–10–

REV. 0

ADG728/ADG729

WRITE OPERATION

When writing to the ADG728/ADG729, the user must begin

with an address byte and R/

W bit, after which the switch will

acknowledge that it is prepared to receive data by pulling SDA

low. This address byte is followed by the 8-bit word. The write

operations for each matrix switch are shown in the figures below.

SCL

SDA

S8

S7

S6

S5

S4

S3

S2

S1

00

1

1

A0

R/

W

STOP

COND

BY

MASTER

ACK

BY

ADG728

START

COND

BY

MASTER

ADDRESS BYTE

DATA BYTE

ACK

BY

ADG728

A1

1

Figure 16. ADG728 Write Sequence

SCL

SDA

S8

S7

S6

S5

S4

S3

S2

S1

00

1

A0

R/

W

STOP

COND

BY

MASTER

ACK

BY

ADG729

START

COND

BY

MASTER

ADDRESS BYTE

DATA BYTE

ACK

BY

ADG729

A1

1

0

Figure 17. ADG729 Write Sequence

READ OPERATION

When reading data back from the ADG728/ADG729, the user

must begin with an address byte and R/

W bit, after which the

matrix switch will acknowledge that it is prepared to transmit data

by pulling SDA low. The readback operation is a single byte

that consists of the eight data bits in the input register. The read

operations for each part are shown in Figures 18 and 19.

SCL

SDA

S8

S7

S6

S5

S4

S3

S2

S1

00

1

A0

R/

W

STOP

COND

BY

MASTER

ACK

BY

ADG728

START

COND

BY

MASTER

ADDRESS BYTE

DATA BYTE

NO ACK

BY

MASTER

A1

1

1

Figure 18. ADG728 Readback Sequence

SCL

SDA

S8

S7

S6

S5

S4

S3

S2

S1

00

1

A0

R/

W

STOP

COND

BY

MASTER

ACK

BY

ADG729

START

COND

BY

MASTER

ADDRESS BYTE

DATA BYTE

NO ACK

BY

MASTER

A1

1

0

Figure 19. ADG729 Readback Sequence