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ADM695 Datasheet(PDF) 6 Page - Analog Devices |
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ADM695 Datasheet(HTML) 6 Page - Analog Devices |
6 / 16 page ADM690–ADM695 REV. A –6– POWER FAIL RESET OUTPUT RESET is an active low output which provides a RESET signal to the Microprocessor whenever VCC is at an invalid level. When VCC falls below the reset threshold, the RESET output is forced low. The nominal reset voltage threshold is 4.65 V (ADM690/ ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693). t 1 t 1 = RESET TIME. V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 V2 V2 V1 V1 t1 V CC LOW LINE RESET Figure 2. Power Fail Reset Timing On power-up RESET will remain low for 50 ms (200 ms for ADM694 and ADM695) after VCC rises above the appropriate reset threshold. This allows time for the power supply and mi- croprocessor to stabilize. On power-down, the RESET output remains low with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. This RESET active time is adjustable on the ADM691/ADM693/ ADM695 by using an external oscillator or by connecting an external capacitor to the OSC IN pin. Refer to Table I and Figure 4. The guaranteed minimum and maximum thresholds of the ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V, while the guaranteed thresholds of the ADM692/ADM693 are 4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695 is, therefore, compatible with 5 V supplies with a +10%, –5% tolerance while the ADM692/ADM693 is compatible with 5 V ± 10% supplies. The reset threshold comparator has approxi- mately 50 mV of hysteresis. The response time of the reset volt- age comparator is less than 1 µs. If glitches are present on the VCC line which could cause spurious reset pulses, then VCC should be decoupled close to the device. In addition to RESET the ADM691/ADM693/ADM695 con- tain an active high RESET output. This is the complement of RESET and is intended for processors requiring an active high RESET signal. Watchdog Timer RESET The watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a RESET pulse is generated. The nominal watchdog timeout period is preset at 1.6 seconds on the ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695 may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. If the “short” period is selected, some systems may be unable to service the watchdog timer immediately after a reset, so the ADM691/ADM693/ADM695 automatically selects the “long” timeout period directly after a reset is issued. The watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on WDI or by VCC falling below the reset threshold. The normal (short) timeout period becomes effective following the first transition of WDI after RESET has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each “long” timeout period (1.6 s). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI) or by connecting it to midsupply. t 2 RESET WDO WDI t 1 = RESET TIME. t 2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD. t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET. t 1 t 1 t 1 t 3 Figure 3. Watchdog Timeout Period and Reset Active Time |
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