REV. A

–5–

ADM706P/R/S/T, ADM708R/S/T

WATCHDOG

TRANSITION

DETECTOR

WATCHDOG

TIMER

1.25V

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

POWER FAIL

OUTPUT (

PFO)

WATCHDOG

OUTPUT(

WDO)

RESET,

(P = RESET)

ADM706

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

MR

70 A

Figure 1. ADM706 Functional Block Diagram

1.25V

POWER FAIL

INPUT (PFI)

POWER FAIL

OUTPUT (

PFO)

RESET

ADM708

RESET

GENERATOR

MR

70 A

RESET

Figure 2. ADM708 Functional Block Diagram

CIRCUIT INFORMATION

Power Fail Reset

The reset output provides a reset (

RESET or RESET) output

the reset threshold. The actual reset threshold voltage is depen-

dent on whether a P/R, S, or T suffix device is used. An internal

timer holds the reset output active for 200 ms after the voltage

reset signal for the microprocessor. It allows time for both the

power supply and the microprocessor to stabilize after power-

up. If a power supply brownout or interruption occurs, the reset

line is similarly activated and remains active for 200 ms after the

supply recovers. If another interruption occurs during an active

reset period, then the reset timeout period continues for an ad-

ditional 200 ms.

as 1 V. This ensures that the microprocessor is held in a stable

shutdown condition as the power supply starts up.

The ADM706P provides an active high reset (RESET) signal;

the ADM706R/S/T provides an active low (

RESET) signal;

while the ADM708R/S/T provides both RESET and

RESET.

Manual Reset

The manual reset input (

MR) allows other reset sources such as

a manual reset switch to generate a processor reset. The input is

effectively debounced by the timeout period (200 ms typical).

The

MR input is TTL/CMOS compatible so it may also be

driven by any logic reset output. If unused, the

MR input may

be tied high or left floating.

RESET

MR

WDO

VRT

VRT

t

RS

t

RS

MR EXTERNALLY

DRIVEN LOW

NOTE: RESET = COMPLEMENT OF

RESET

Figure 3.

RESET, MR and WDO Timing

Watchdog Timer (ADM706)

The watchdog timer circuit may be used to monitor the activity

of the microprocessor in order to check that it is not stalled in

an indefinite loop. An output line on the processor is used to

toggle the Watchdog Input (WDI) line. If this line is not toggled

within the timeout period (1.6 sec), the watchdog output

(

WDO) is driven low. The WDO output may be connected to a

nonmaskable interrupt (NMI) on the processor. Therefore, if

the watchdog timer times out, an interrupt is generated. The in-

terrupt service routine should then be used to rectify the

problem.

The watchdog timer is cleared by either a high-to-low or by a

low-to-high transition on WDI. Pulses as narrow as 50 ns are

detected. The timer is also cleared by RESET/

RESET going

active. Therefore the watchdog timeout period begins after reset

goes inactive.

whether or not the watchdog timer has timed out. Normally

this would generate an interrupt but it is overridden by RESET/

RESET going active.

The watchdog monitor can be deactivated by floating the

Watchdog Input (WDI). The

WDO output can now be used as

the reset threshold.

t

WP

t

WD

WDI

WDO

RESET

t

RS

RESET EXTERNALLY

TRIGGERED BY

MR

t

WD

t

WD

Figure 4. Watchdog Timing