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ADM800MARW Datasheet(PDF) 9 Page - Analog Devices |
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ADM800MARW Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page ADM691A/ADM693A/ADM800L/M –9– REV. 0 7 OSC SEL OSC IN 8 ADM69_A ADM800_ COSC Figure 18d. Internal Oscillator (100 ms Watchdog) WDI WDO t 1 RESET t 1 = RESET TIME. t 2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD. t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET. t 1 t 1 t 2 t 3 Figure 19. Watchdog Timing CE Gating and RAM Write Protection All products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when VCC is at an invalid level. There are two additional pins, CEIN and CEOUT, that control the Chip Enable or Write inputs of CMOS RAM. When VCC is present, CEOUT is a buffered rep- lica of CEIN, with a 5 ns propagation delay. When VCC falls be- low the reset voltage threshold, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an in- valid level. Similar protection of EEPROMs can be achieved by using the CEOUT to drive the Store or Write inputs of an EEPROM, EAROM, or NOVRAM. Power Fail Warning Comparator An additional comparator is provided for early warning of fail- ure in the microprocessor’s power supply. The Power Fail Input (PFI) is compared to an internal +1.25 V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider that senses either the unregulated dc input to the system’s 5 V regu- lator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.25 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shut- down proce- dure executed before power is lost. R2 PFO 1.25V POWER FAIL INPUT POWER FAIL OUTPUT R1 INPUT POWER Figure 20. Power Fail Comparator Table III. Input and Output Status in Battery Backup Mode Signal Status VBATT Supply Current is <1 µA. VOUT VOUT is connected to VBATT via an internal PMOS switch. VCC Switchover comparator monitors VCC for active switchover. GND 0 V. BATT ON Logic High. The open circuit voltage is equal to VOUT. LOW LINE Logic Low. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. PFI The Power Fail Comparator remains active in the battery-backup mode for VCC ≥ VBATT –1.2 V. With VCC lower than this, PFO is forced low. PFO The Power Fail Comparator remains active in the battery-backup mode for VCC ≥ V BATT –1.2 V. With VCC lower than this, PFO is forced low. WDI WDI is ignored. CEOUT Logic High. The open circuit voltage is equal to VOUT. CEIN High Impedance. WDO Logic High. The open circuit voltage is equal to VOUT. RESET Logic Low. RESET High Impedance. |
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