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AOZ1039DI Datasheet(PDF) 9 Page - Alpha & Omega Semiconductors |
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AOZ1039DI Datasheet(HTML) 9 Page - Alpha & Omega Semiconductors |
9 / 13 page AOZ1039DI Rev. 1.2 September 2011 www.aosmd.com Page 9 of 13 If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum capacitors are recommended as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, the output capacitor could be overstressed. Loop Compensation The AOZ1039DI employs peak current mode control for easy of use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It also greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in the frequency domain. The pole is dominant pole can be calculated by: The zero is a ESR zero due to the output capacitor and its ESR. It is can be calculated by: where; CO is the output filter capacitor, RL is load resistor value, and ESRCO is the equivalent series resistance of output capacitor. The compensation design shapes the converter control loop transfer function to get desired gain and phase. Several different types of compensation network can be used for the AOZ1039DI. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high- bandwidth control loop. In the AOZ1039DI, FB pin and COMP pin are the inverting input and the output of internal error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: where; GEA is the error amplifier transconductance, which is 200 x 10-8 A/V, GVEA is the error amplifier voltage gain, which is 500 V/V, and CC is the compensation capacitor in Figure 1. The zero given by the external compensation network, capacitor CC and resistor RC, is located at: To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover is the also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concerns. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: where; fC is the desired crossover frequency. For best performance, fC is set to be about 1/10 of the switching frequency; VFB is 0.8V, GEA is the error amplifier transconductance, which is 200 x 10-8 A/V, and GCS is the current sense circuit transconductance, which is 8.3 A/V ΔV O ΔI L ESR CO × = I CO_RMS ΔI L 12 ---------- = f P 1 1 2 π C O R L × × ----------------------------------- = f Z 1 1 2 π C O ESR CO × × ------------------------------------------------ = f P 2 G EA 2 π C C G VEA × × ------------------------------------------- = f Z 2 1 2 π C C R C × × ----------------------------------- = R C f C V O V FB ---------- 2 π C C × G EA G CS × ------------------------------ × × = |
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