ADP1073

–10–

REV. 0

R1

R2









The design criteria for the step-down application also apply to

the positive-to-negative converter. The output voltage should be

limited to |6.2 V| and D1 must be a Schottky diode to prevent

excessive power dissipation in the ADP1073.

Negative-to-Positive Conversion

The circuit of Figure 18 converts a negative input voltage to a

positive output voltage. Operation of this circuit configuration is

similar to the step-up topology of Figure 16, except that the cur-

rent through feedback resistor R1 is level-shifted below ground

However, diode D2 level-shifts the base of Q1 about 0.6 V below

also reduces the circuit’s output voltage sensitivity to tempera-

ture, which would otherwise be dominated by the –2 mV/

°C V

BE

contribution of Q1. The output voltage for this circuit is deter-

mined by the formula:

R1

R2









Unlike the positive step-up converter, the negative-to-positive

converter’s output voltage can be either higher or lower than the

input voltage.

D1

1N5818

SW1

FB

SW2

GND

ADP1073

L1

D2

1N4148

C2

R1

Q1

2N3906

AO

SET

NC

NC

R2

10k

POSITIVE

OUTPUT

NEGATIVE

INPUT

Figure 18. A Negative-to-Positive Converter

Limiting the Switch Current

ited with a single resistor. This current limiting action occurs on

a pulse by pulse basis. This feature allows the input voltage to

vary over a wide range without saturating the inductor or ex-

ceeding the maximum switch rating. For example, a particular

design may require peak switch current of 800 mA with a 2.0 V

1.6 A. The ADP1073 limits switch current to 1.5 A and thereby

protects the switch, but the output ripple will increase. Selecting

the proper resistor will limit the switch current to 800 mA, even

switch current is shown in Figure 4.

when the ADP1073 goes into continuous conduction mode. This

occurs in the step-up mode when the following condition is met:

<

1

1– DC

where DC is the ADP1073’s duty cycle.

When this relationship exists, the inductor current does not go

all the way to zero during the time that the switch is OFF. When

the switch turns on for the next cycle, the inductor current

begins to ramp up from the residual level. If the switch ON time

remains constant, the inductor current will increase to a high

level (see Figure 19). This increases output ripple and can

require a larger inductor and capacitor. By controlling switch

tained at the design values. Figure 20 illustrates the action of the

Q1 is the ADP1073’s internal power switch, which is paralleled

by sense transistor Q2. The relative sizes of Q1 and Q2 are

internal 80

Ω resistor and through the R

resistors parallel the base-emitter junction of the oscillator-

exceeds 0.6 V, Q3 turns on and terminates the output pulse. If

only the 80

Ω internal resistor is used (i.e., the I

The delay through the current limiting circuit is approximately

2

µs. If the switch ON time is reduced to less than 5 µs, accu-

racy of the current trip point is reduced. Attempting to program

a switch ON time of 2

µs or less will produce spurious responses

in the switch ON time. However, the ADP1073 will still provide

a properly regulated output voltage.