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ADP3088 Datasheet(PDF) 8 Page - Analog Devices |
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ADP3088 Datasheet(HTML) 8 Page - Analog Devices |
8 / 11 page ADP3088 –8– REV. PrK PRELIMINARY TECHNICAL DATA amplifier, its frequency response limitation (i.e., as ad- equately modeled by a capacitance from output to ground) its external termination impedance (i.e., the compensation, that may or may not include DC feedback), the modulator transconductance, and the power converter's termination impedance (i.e., the output capacitor and load resistance). Since the ADP3088 has a current controlled loop, the par- ticular inductor value does not by first order consideration affect small signal stability. However, slew rate limitations as discussed earlier - a large signal limitation consideration - set boundaries that are often relevant for optimizing com- pensation of the feedback loop. If the compensation of the current control signal, i.e., the COMP pin, is designed to promote a current response that is faster than the inductor current can slew, then when a step load is applied the con- trol signal will tend to initially respond in excess (of the actual current change that is occurring) and then allow an overshoot of the current and output voltage as it is delayed in correcting its excess. For conventional loads, the following describes how the frequency corners (poles and zeroes) are positioned or should be chosen to optimize the loop gain, beginning in the low frequency spectrum: 1. The DC loop gain is limited by the applied load resis- tance and the output resistance of the error amplifier, but it is not important to determine how high the DC gain is. 2. Two poles in the LF spectrum begin to roll off the gain, one determined by the load resistance and output ca- pacitor, CO, and the other by the error amplifier's out- put resistance and its termination capacitance - the equivalent feedback capacitance and the added com- pensation capacitance CHF; determining the location of these poles is not relevant to compensation design - it suffices to know that both are decades below the cross- over frequency. 3. A lead network is especially desirable for a variable out- put voltage application in order to keep a fairly constant crossover frequency and phase margin for all output voltages; if used, this lead network consists of simply a capacitor, CFF, in parallel with the upper feedback di- vider resistor, RA; this creates a closely spaced zero/pole pair that provides a gain boost before crossover so that, above the pole frequency, the loop gain and phase are similar for all output voltages; if the lead network is used for a fixed voltage application, the pole should be cho- sen to align with the following described zero; for vari- able voltage applications, the maximum frequency of the pole should be placed as high as is comfortable with- out substantially degrading phase margin (e.g., not within an octave or, more conservatively, a half decade of the crossover frequency). 4. A zero turns the gain rolloff back to 1-pole sufficiently in advance of the crossover frequency to create ample phase margin, e.g., half a decade; the zero could feasi- bly be that of the output capacitor itself - i.e., the zero formed by the ESR and the capacitance CO - but that is both unlikely (since the zero frequency will likely be higher than where the loop zero is desired) and gener- ally imprudent (since the loop performance would de- pend on the stability of the ESR, which often is poor or unknown); as recommended, the zero, fZ, is created by an RC circuit terminating the COMP pin (a resistor, RC, in series with a capacitor, CC), while the capacitance terminating the error amplifier, CHF, forms a pole, fP, with RC to cancel the zero of the output capacitor, or, if the zero is well above the crossover frequency, as may be the case when using an MLC output capacitor, that pole is set high enough above the crossover frequency, again e.g., half a decade, so that it doesn't cut substan- tially into the phase margin at crossover, but still ensures continued gain rolloff so that the gain margin is accept- ably high; note that the previous guidelines suggest that CC ≥ 10 × C HF. 5. The gain crosses 0 dB (unity) at a crossover frequency that is typically a tenth and advisably not greater than a fourth of the switching frequency - one primary reason for this approximate upper limit being the extra phase margin loss due to the switching interval that is not pre- dicted by the linear model. Assuming no lead network is used, the open loop gain is given by: COMP O OL OUT V ZZ A V 2 600 µ× × Ω ≈ (15) where VOUT is the nominal DC level. This equation to- gether with the preceding recommendations should suffice to determine compensation component selection for users familiar with loop design. This begins with deciding the crossover frequency, fC, evaluating the impedances at that frequency, and setting the open loop gain, AOL, to unity. By example, fC = 125 kHz is chosen. Assuming a well chosen CHF as described previously - i.e., such that it creates a pole well above crossover or approxi- mately matches the zero of the output capacitor, the fol- lowing equation approximates the calculation of the crossover frequency: () () 1 1 150 / 1 21 / Z C kA f k f kA k +Ω × × =+ Ω× (16) where k1 = CO×VOUT/RC and fZ = 1/2 πRCCC - the zero frequency set by the compensation - and the units are shown with the constants in the equation for clarification. The preceding equation cannot readily be solved in terms of k1, but it can be solved closely enough by a few iterations beginning with values for k1 around 1×10 9 (FA). For the example below, set the zero about a half decade below fC as previously advised, that is, choose fZ ~ fC / √10 = 40 kHz. Using the previously stated values for fZ and fC, the value of k1 = 800 p(FA) satisfies the equation. RA and RB are pre- sumed to be already chosen per earlier guidelines to set the output voltage. As an example, RA = RB = 10 k Ω (imply- ing an output voltage of 2.5 V). Similarly it is presumed that CO was chosen; let CO = 15 µF. Then, finally, RC and then also CC can be determined by rearrangement of simple formulas previously given. The example yields RC ~ 47 k Ω and CC ~ 82 pF. Assuming an MLC output capaci- |
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