REV. 0

ADP3342

–7–

THEORY OF OPERATION

The new anyCAP LDO ADP3342 uses a single control loop for

regulation and reference functions. The output voltage is sensed

by a resistive voltage divider consisting of R1 and R2. Feedback

is taken from this network by way of a series diode (D1) and a

second resistor divider (R3 and R4) to the input of an amplifier.

PTAT

NONINVERTING

WIDEBAND

DRIVER

INPUT

Q1

ADP3342

COMPENSATION

CAPACITOR

ATTENUATION

R1

D1

R2

R3

R4

OUTPUT

PTAT

CURRENT

(a)

GND

VCC

Figure 2. Control Loop Functional Block Diagram

A very high gain error amplifier is used to control this loop. The

amplifier is constructed in such a way that at equilibrium it

produces a large, temperature proportional input “offset voltage”

that is repeatable and very well controlled. The temperature

proportional offset voltage is combined with the complementary

diode voltage to form a “virtual bandgap” voltage, implicit in

the network, although it never appears explicitly in the circuit.

Ultimately, this patented design makes it possible to control the

loop with only one amplifier. This technique also improves the

noise characteristics of the amplifier by providing more flexibility

on the trade-off of noise sources that leads to a low noise design.

The R1, R2 divider is chosen in the same ratio as the bandgap

voltage to the output voltage. Although the R1, R2 resistor

divider is loaded by the diode D1 and a second divider consisting

of R3 and R4, the values can be chosen to produce a temperature

stable output. This unique arrangement specifically corrects for

the loading of the divider so that the error resulting from base

current loading in conventional circuits is avoided.

The patented amplifier controls a new and unique noninverting

driver that drives the pass transistor, Q1. The use of this special

noninverting driver enables the frequency compensation to include

the load capacitor in a pole splitting arrangement to achieve reduced

sensitivity to the value, type and ESR of the load capacitance.

Most LDOs place very strict requirements on the range of ESR

values for the output capacitor because they are difficult to stabilize

due to the uncertainty of load capacitance and resistance. More-

over, the ESR value, required to keep conventional LDOs stable,

changes depending on load and temperature. These ESR limitations

make designing with LDOs more difficult because of their unclear

specifications and extreme variations over temperature.

With the ADP3342 anyCAP LDO, this is no longer true. It can

be used with virtually any good quality capacitor, with no con-

straint on the minimum ESR. This innovative design allows the

circuit to be stable with just a small 1

µF capacitor on the output.

Additional advantages of the pole splitting scheme include superior

line noise rejection and very high regulator gain which leads to

excellent line and load regulation.

Additional features of the circuit include current limit and thermal

shutdown and noise reduction.

APPLICATION INFORMATION

PC Application—VCCVID

The ADP3342 has been optimized for PC applications that

require a 1.2 V output for powering the voltage identification

rail, VCCVID. The rail from which the output draws current,

the IN pin, is separated from the rail that powers the IC, the

VCC pin. This allows a higher efficiency design when, as

recommended for the IMVP-3 application, the VCC pin is

connected to a 3.3 V supply to power the IC adequately, and

the IN pin is connected to a 1.8 V supply. The efficiency is

nearly 60% in this case.

Capacitor Selection

As with any voltage regulator, output transient response is a

function of the output capacitance. The ADP3342 is stable with

a wide range of capacitor values, types and ESR (anyCAP).

A capacitor as low as 1

µF is all that is needed for stability; larger

capacitors can be used if high output current surges are anticipated.

The ADP3342 is stable with extremely low ESR capacitors (ESR

≈ 0),

such as multilayer ceramic capacitors (MLCC) or OSCON.

Note that the effective capacitance of some capacitor types may

fall below the minimum at cold temperature. Ensure that the

capacitor provides more than 1

µF at minimum temperature.

Input Bypass Capacitor

An input bypass capacitor is not strictly required but is advisable

in any application involving long input wires or high source

impedance. Connecting a 1

µF capacitor from IN to ground reduces

the circuit's sensitivity to PC board layout. If a larger value output

capacitor is used, then a larger value input capacitor is also

recommended.

Power Good Monitoring Function

The PWRGD pin does not monitor the output voltage directly,

but rather detects whether the internal PNP pass transistor is being

modulated by the regulation loop. This means of detecting PWRGD,

rather than using a voltage threshold detection, provides an inherent

and desirable delay in asserting the PWRGD signal. During

startup or overload, the regulation loop is not in control, so the

PWRGD pin is low.

Shutdown Mode

Applying a TTL high signal to the shutdown (

SD) pin or tying

it to the input pin, will turn the output ON. Pulling

SD down to

0.4 V or below, or tying it to ground will turn the output OFF.

In shutdown mode, quiescent current is reduced.

Paddle-Under-Lead Package

The ADP3342 uses a patented paddle-under-lead package design

to ensure the best thermal performance in an MSOP-8 footprint.

This new package uses an electrically isolated die attach that

allows all pins to contribute to heat conduction. This technique

reduces the thermal resistance to 110

°C/W on a 4-layer board as

compared to >160

°C/W for a standard MSOP-8 leadframe.

Thermal Overload Protection

The ADP3342 is protected against damage due to excessive power

dissipation by its thermal overload protection circuit which limits

the die temperature to a maximum of 165

°C. Under extreme

conditions (i.e., high ambient temperature and power dissipation)

where die temperature starts to rise above 165

°C, the output current

is reduced until the die temperature has dropped to a safe level.

The output current is restored when the die temperature is reduced.