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DCR4500A36 Datasheet(PDF) 7 Page - Dynex Semiconductor |
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DCR4500A36 Datasheet(HTML) 7 Page - Dynex Semiconductor |
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7 / 10 page  7/10 www.dynexsemi.com Fig.10 Multi-cycle surge current Fig.11 Single-cycle surge current Fig.12 Stored charge Fig.13 Reverse recovery current 1 10 100 1 10 100 Number of cycles Conditions: Tcase = 125°C VR =0 Pulse width = 10ms 0 20 40 60 80 100 120 140 160 180 200 1 10 100 Pulse width, tP - (ms) 0 3 6 9 12 15 18 21 24 27 30 I 2t ITSM Conditions: Tcase= 125°C VR = 0 half-sine wave 0 5000 10000 15000 20000 25000 0 5 10 15 20 25 30 Rate of decay of on-state current, di/dt - (A/us) Qs max = 4874.7*(di/dt) 0.4822 Qs min = 2920.8*(di/dt) 0.581 Conditions: Tj = 125ºC, VR peak ~ 2500V VRM ~ 1700V snubber as required to control reverse voltage 0 100 200 300 400 500 600 700 0 5 10 15 20 25 30 Rate of decay of on-state current, di/dt - (A/us) Conditions: Tj = 125ºC, VR peak ~ 2500V VRM ~ 1700V snubber as required to control reverse voltage IRR max = 57.242*(di/dt) 0.7466 IRR min = 41.99*(di/dt) 0.7893 |
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