REV. 0

ADP3410

–9–

delay from the

DRVLSD input to the DRVL output is about

30 ns.

Synchronous Rectifier Monitor

The synchronous rectifier monitor provides a TTL output signal

for use by the PWM controller. The SRMON output follows the

DRVL signal when the low-side driver is enabled and goes high

when the low-side driver is shut down.

Shutdown

The shutdown input is used for power management. If the cir-

cuits running off of the buck converter are not needed, the

ADP3410 can be shut down to conserve power.

When the

SD pin is high, the ADP3410 is enabled for normal

operation. Pulling the

SD pin low forces the VCCGD, DRVH

and DRVL outputs low turning the buck converter OFF and

reducing the VCC supply current to less than 10

µA.

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both FET

driver outputs low during VCC supply ramp up. The UVLO

logic becomes active and in control of the driver outputs at a

supply voltage of 1.5 V. The UVLO circuit will wait until the

VCC supply has reached a voltage high enough to bias logic

level FETs fully ON, around 4.4 V, before releasing control

of the drivers to the PWM input.

VCC Good

The power ready signal, VCCGD, indicates the status of the

VCC supply. When the device is in UVLO, the VCCGD output

is pulled low by an NMOS transistor. Upon exiting UVLO mode,

the VCCGD pin is pulled up to VCC with a 5

Ω PMOS transis-

tor capable of sourcing current to external load circuits. As can

be seen from the block diagram, the UVLO comparator output

and the

SD signal are ANDed together to become the VCCGD

output, so when the device is put into shutdown the VCCGD

output will be low regardless of the VCC voltage.

Thermal Shutdown

The thermal shutdown circuit protects the ADP3410 against

damage due to excessive power dissipation. Under extreme

conditions, high ambient temperature and high-power dissipation,

the die temperature can rise up to the over-temperature trip

point of 165

°C. If the die temperature exceeds 165°C, the

thermal shutdown circuit will turn the output drivers OFF. The

drivers will remain disabled until the junction temperature has

decreased by 10

°C, at which point the drivers are enabled again.

APPLICATION INFORMATION

Supply Capacitor Selection

For the supply input (VCC) of the ADP3410, a local bypass

capacitor is recommended to reduce the noise and to supply

some of the peak currents drawn. Use a 5

µF to 10 µF, low ESR

capacitor. Multilayer ceramic chip (MLCC) capacitors provide

the best combination of low ESR and small size and can be

obtained from the following vendors:

Murata

GRM235Y5V106Z16 http://www.murata.com

Taiyo-Yuden EMK325F106ZF

http://www.t-yuden.com

Tokin

C23Y5V1C106ZP

http://www.tokin.com

A lower cost alternative may be to use a 5

µF to 10 µF tantalum

capacitor with a small (1

µF) ceramic in parallel. Keep the

ceramic capacitor as close as possible to the ADP3410.

Bootstrap Circuit

and a Schottky diode, D1, as shown in Figure 2. Selecting these

components can be done after the high-side FET has been chosen.

The bootstrap capacitor must have a voltage rating that is able

to handle the maximum battery voltage plus 5 V. A minimum

50 V rating is recommended. The capacitance is determined

using the following equation:

C

Q

V

BST

GATE

BST

=

∆

(1)

∆V

For example, the IRF7811 has a total gate charge of about

20 nC. For an allowed droop of 200 mV, the required bootstrap

capacitance is 100 nF. Look for a good quality ceramic capacitor.

A Schottky diode is recommended for the bootstrap diode due

to its low forward drop, which maximizes the drive available for

the high-side FET. The bootstrap diode must have a minimum

40 V rating to withstand the maximum battery voltage plus 5 V.

The average forward current can be estimated by:

IQ

f

F AVG

GATE

MAX

(2)

The peak surge current rating should be checked in circuit since

this is dependent on the source impedance of the 5 V supply,

Setting the OVP Threshold

The ADP3410 can shut down the high-side FET drive when the

OVPSET input exceeds the threshold voltage. The voltage at

the values for Ra and Rb shown in Figure 2. The threshold for

the OVP is calculated using:

VV

Ra

Rb

OVP

=×

+









12

1

.

(3)

In order to minimize the bias current error, Rb should be less

than or equal to 24 k

Ω. By selecting a value for Rb ≤ 24 kΩ and

solving for Ra gives the following formula:

Ra

V

V

Rb

OVP

=−











 ×

12

1

.

(4)

Note that the minimum the OVP threshold can be is 1.2 V when

Ra is zero.

Delay Capacitor Selection

when the low-side FET drive turns off and when the high-side

drive starts to turn on. The delay capacitor adds 1 ns/pF of

additional time to the 20 ns of fixed delay.

If a delay capacitor is required, a good quality ceramic capacitor

with an NPO or COG dielectric or a good quality mica capacitor

should be used. Both types of capacitors are available in the

1 pF to 100 pF range and have excellent temperature and

leakage characteristics.