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ADP3604 Datasheet(PDF) 4 Page - Analog Devices |
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ADP3604 Datasheet(HTML) 4 Page - Analog Devices |
4 / 8 page ADP3604 REV. 0 –4– APPLICATION INFORMATION The ADP3604 uses a charge pump to generate a negative out- put voltage from a positive input supply. To understand the operation of the ADP3604, a review of a basic switch capacitor building block is helpful. f RL V1 V2 C1 C2 AB Figure 11. Basic Switch Capacitor Circuit In Figure 11, when the switch is in the A position, capacitor C1 will be charged to voltage V1. The total charge on C1 will be q1 = C1V1. The switch then moves to the B position, discharging C1 to voltage V2. After this discharge time, the charge on C1 is q2 = C1V2. The amount of charge transferred from the source, V1, to the output, V2 is: ∆q = q1 – q2 = C1(V1 – V2) If the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is: I = f ∆q = fC1(V1 – V2) To obtain an equivalent resistance for the switched-capacitor network we can rewrite this equation in terms of voltage and impedance equivalence: I = (V1 – V2)/(1/fC1) = (V1 – V2)/REQUIV where REQUIV is defined as : REQUIV = 1/fC1 Figure 11 equivalent circuit now can be drawn as shown in Figure 12. RL V1 V2 C2 REQUIV REQUIV = 1 fC1 Figure 12. Basic Switch Capacitor Equivalent Circuit THEORY OF OPERATION A switched capacitor principle is used in the ADP3604 to gener- ate a negative voltage from a positive input voltage. An on-board oscillator generates two phase clocks to control a switching net- work which transfers charge between the storage capacitors. The basic principle behind the voltage inversion scheme is illus- trated in Figures 13 and 14. VIN S2 CP S1 VOUT S3 S4 COUT Figure 13. Switch Configuration Charging the Pump Capacitor During phase one, S1 and S2 are ON charging the pump ca- pacitor to the input voltage. Before the next phase begins, S1 and S2 are turned OFF as well as S3 and S4 to prevent any overlap. S3 and S4 are turned ON during the second phase (see Figure 14) and charge stored in the pump capacitor is trans- ferred to the output capacitor. VIN S2 CP S1 VOUT S3 S4 COUT Figure 14. Switch Configuration Charging the Output Capacitor During the second phase, the positive terminal of the pump capacitor is connected to ground and the negative terminal is connected to the output resulting in a voltage inversion at the output terminal. Output regulation is done by adjusting the ON resistance of the S3 through the feedback control loop. The ADP3604 alternately charges CP to the input voltage when CP is switched in parallel with the input supply, and then trans- fers charge to COUT when CP is switched in parallel with COUT. Switching occurs at 120 kHz rate. During the time that CP is charging, the peak current is approximately 2 times the output current. During the time that CP is delivering charge to COUT, the supply current drops down to about 2 mA. An input supply bypass capacitor will supply part of the peak input current drawn by the ADP3604, and average out the current drawn from the supply. A minimum input supply bypass capacitor of 1 µf, preferably a low ESR capacitor such as tantalum or multilayer ceramic chip capacitor, is recommended. A large capacitor may be desirable in some cases, for example when the input supply is connected to the ADP3604 through long leads, or when the pulse current drawn by the device might effect other circuitry through supply coupling. The output capacitor, COUT, is alternately charged to the CP voltage when CP is switched in parallel with COUT. The ESR of the COUT introduces steps in the VOUT waveform whenever the charge pump charges COUT. This tends to increase VOUT ripple. Ceramic or tantalum capacitors are recommended for COUT if minimum ripple is desired. The ADP3604 can operate with a range of capacitors from 1 µf to 100 µf and larger without any stability problems. However, all tested parameters are obtained using 10 µf multilayer ceramic capacitors. In most applications, IR drops due to printed circuit board traces do not present a problem. In this case, VSENSE is tied to the output at a convenient pcb location not far from the VOUT. However, if a reduction in IR drops or improvement in load regulation is desired, the sense line can be used to monitor the output voltage at the load. To avoid excessive noise pickup, the VSENSE line should be as short as possible and away from any noisy line. While the exact values of the CIN and COUT are not critical, good quality, low ESR capacitors such as solid tantalum and multi- layer ceramic capacitors are recommended to minimize voltage losses at high currents. For a given load current, factors affecting the output voltage performance in Figure 15 are: • Pump (C2) and the output (C3) capacitance • ESR of the C2 and C3 |
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