This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

5

REV. PrB

For current information contact Analog Devices at 800/262-5643

ADSP-21160N

April 2002

PRELIMINARY TECHNICAL DATA

transfers). Programs can be downloaded to the

ADSP-21160N using DMA transfers. Asynchronous

off-chip peripherals can control two DMA channels using

DMA Request/Grant lines (

DMAR1–2, DMAG1–2).

Other DMA features include interrupt generation upon

completion of DMA transfers, two-dimensional DMA, and

DMA chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-21160N offers powerful features tailored to

multiprocessing DSP systems as shown in Figure 4. The

external port and link ports provide integrated glueless mul-

tiprocessing support.

The external port supports a unified address space (see

Figure 2) that allows direct interprocessor accesses of each

ADSP-21160N’s internal memory. Distributed bus arbitra-

tion logic is included on-chip for simple, glueless connection

of systems containing up to six ADSP-21160Ns and a host

processor. Master processor changeover incurs only one

cycle of overhead. Bus arbitration is selectable as either fixed

or rotating priority. Bus lock allows indivisible read-mod-

ify-write sequences for semaphores. A vector interrupt is

provided for interprocessor commands. Maximum

throughput for interprocessor data transfer is 380M bytes/s

over the external port. Broadcast writes allow simultaneous

transmission of data to all ADSP-21160Ns and can be used

to implement reflective semaphores.

Six link ports provide for a second method of multiprocess-

ing communications. Each link port can support

communications to another ADSP-21160N. Using the

links, a large multiprocessor system can be constructed in a

2D or 3D fashion. Systems can use the link ports and cluster

multiprocessing concurrently or independently.

Link Ports

The ADSP-21160N features six 8-bit link ports that provide

additional I/O capabilities. With the capability of running

at 95 MHz rates, each link port can support 95M bytes/s.

Link port I/O is especially useful for point-to-point inter-

processor communication in multiprocessing systems. The

link ports can operate independently and simultaneously.

Link port data is packed into 48- or 32-bit words, and can

be directly read by the core processor or DMA-transferred

to on-chip memory. Each link port has its own double-buff-

ered input and output registers. Clock/acknowledge

handshaking controls link port transfers. Transfers are pro-

grammable as either transmit or receive.

Serial Ports

The ADSP-21160N features two synchronous serial ports

that provide an inexpensive interface to a wide variety of

digital and mixed-signal peripheral devices. The serial ports

can operate up to half the clock rate of the core, providing

each with a maximum data rate of 47.5M bit/s. Independent

transmit and receive functions provide greater flexibility for

serial communications. Serial port data can be automati-

Figure 2. ADSP-21160N Memory Map

0x00 0000

0x02 0000

0x04 0000

0x08 0000

0x10 0000

0x20 0000

0x30 0000

0x40 0000

0x50 0000

0x60 0000

0x70 0000

0x7F FFFF

0x80 0000

0xFFFF FFFF

Internal

Memory

Space

External

Memory

Space

IOP Reg’s

Long Word

Normal Word

Short Word

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Internal

Space

Broadcast

All DSPs

Bank 0

Bank 1

Bank 2

Bank 3

Nonbanked

Memory

(ID = 011)

(ID = 100)

Memory

(ID = 101)

Memory

Memory

(ID = 110)

Write to

(ID = 111)

Memory

(ID = 010)

Memory

(ID = 001)

Multiprocessor

Memory

Space

Figure 3. ADSP-21160N External Data Alignment

Options

DATA63–0

63

55

47

39

31

23

15

7

0

RDH/WRH

RDL/WRL

EPROM

16-BIT PACKED

32-BIT PACKED

64-BIT TRANSFER FOR 40-BIT EXTENDED PRECISION

64-BIT TRANSFER FOR 48-BIT INSTRUCTION FETCH

RESTRICTED DMA, HOST, EPROM DATA ALIGNMENTS:

64-BIT LONG WORD, SIMD, DMA, IOP REGISTER TRANSFERS

BYTE 0

BYTE 7

32-BIT NORMAL WORD (EVEN ADDRESS)

32-BIT NORMAL WORD (ODD ADDRESS)