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ADSP-2186L Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-2186L Datasheet(HTML) 11 Page - Analog Devices |
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11 / 34 page  ADSP-2186L –11– REV. A If Go Mode is enabled, the ADSP-2186L will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2186L is performing an external memory access when the external device asserts the BR signal, it will not three- state the memory interfaces or assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, reenables the output drivers and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-2186L is ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-2186L deasserts BG and BGH and executes the external memory access. Flag I/O Pins The ADSP-2186L has eight general purpose programmable input/ output flag pins. They are controlled by two memory mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-2186L’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, the ADSP-2186L has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1 and PF2 are also used for device configu- ration during reset. BIASED ROUNDING A mode is available on the ADSP-2186 or ADSP-2186L to allow biased rounding in addition to the normal unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased round- ing operations occur. When the BIASRND bit is set to 1, biased rounding occurs instead of the normal unbiased rounding. When operating in biased rounding mode all rounding operations with MR0 set to 0x8000 will round up, rather than only rounding up odd MR1 values. For example: Table VII. Biased Rounding Example MR Value Biased Unbiased Before RND RND Result RND Result 00-0000-8000 00-0001-8000 00-0000-8000 00-0001-8000 00-0002-8000 00-0002-8000 00-0000-8001 00-0001-8001 00-0001-8001 00-0001-8001 00-0002-8001 00-0002-8001 00-0000-7FFF 00-0000-7FFF 00-0000-7FFF 00-0001-7FFF 00-0001-7FFF 00-0001-7FFF This mode only has an effect when the MR0 register contains 0x8000; all other rounding operations work normally. This mode allows more efficient implementation of bit-specified algorithms that use biased rounding, for example the GSM speech compression routines. Unbiased rounding is preferred for most algorithms. Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer Control register. INSTRUCTION SET DESCRIPTION The ADSP-2186L assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits: • The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. • Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. • The syntax is a superset ADSP-2100 Family assembly lan- guage and is completely source and object code compatible with other family members. Programs may need to be relo- cated to utilize on-chip memory and conform to the ADSP- 2186L’s interrupt vector and reset vector map. • Sixteen condition codes are available. For conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. • Multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM The ADSP-2186L has on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If using a passive method of maintaining mode information (as discussed in Setting Memory Modes), it does not matter that the mode information is latched by an emulator reset. However, if using the RESET pin as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. One method of ensuring that the values located on the mode pins are the desired values is to construct a circuit like the one shown in Figure 9. This circuit forces the value located on the Mode A pin to logic low, regardless if it latched via the RESET or ERESET pin. |
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