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ADSP-2163KS-66 Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-2163KS-66 Datasheet(HTML) 5 Page - Analog Devices |
5 / 39 page REV. 0 ADSP-216x –5– The ADSP-216x serial ports offer the following capabilities: Bidirectional—Each SPORT has a separate, double-buffered transmit and receive function. Flexible Clocking—Each SPORT can use an external serial clock or generate its own clock internally. Flexible Framing—The SPORTs have independent framing for the transmit and receive functions; each function can run in a frameless mode or with frame synchronization signals inter- nally generated or externally generated; frame sync signals may be active high or inverted, with either of two pulsewidths and timings. Different Word Lengths—Each SPORT supports serial data word lengths from 3 to 16 bits. Companding in Hardware—Each SPORT provides optional A-law and µ-law companding according to CCITT recommen- dation G.711. Flexible Interrupt Scheme—Receive and transmit functions can generate a unique interrupt upon completion of a data word transfer. Autobuffering with Single-Cycle Overhead—Each SPORT can automatically receive or transmit the contents of an entire circular data buffer with only one overhead cycle per data word; an interrupt is generated after the transfer of the entire buffer is completed. Multichannel Capability (SPORT0 Only)—SPORT0 pro- vides a multichannel interface to selectively receive or transmit a 24-word or 32-word, time-division multiplexed serial bit stream; this feature is especially useful for T1 or CEPT interfaces, or as a network communication scheme for multiple processors. Alternate Configuration—SPORT1 can be alternatively configured as two external interrupt inputs ( IRQ0, IRQ1) and the Flag In and Flag Out signals (FI, FO). Interrupts The ADSP-216x’s interrupt controller lets the processor re- spond to interrupts with a minimum of overhead. Up to three external interrupt input pins, IRQ0, IRQ1 and IRQ2, are pro- vided. IRQ2 is always available as a dedicated pin; IRQ1 and IRQ0 may be alternately configured as part of Serial Port 1. The ADSP-216x also supports internal interrupts from the timer and the serial ports. The interrupts are internally prioritized and individually maskable (except for RESET which is nonmaskable). The IRQx input pins can be programmed for either level- or edge-sensitivity. The interrupt priorities for each ADSP-216x processor are shown in Table II. Table II. Interrupt Vector Addresses and Priority Interrupt ADSP-216x Interrupt Source Vector Address RESET Startup 0x0000 IRQ2 or Power-Down 0x0004 (High Priority) SPORT0 Transmit 0x0008 SPORT0 Receive 0x000C SPORT1 Transmit or IRQ1 0x0010 SPORT1 Receive or IRQ0 0x0014 Timer 0x0018 (Low Priority) The ADSP-216x uses a vectored interrupt scheme: when an interrupt is acknowledged, the processor shifts program control to the interrupt vector address corresponding to the interrupt received. Interrupts can be optionally nested so that a higher priority interrupt can preempt the currently executing interrupt service routine. Each interrupt vector location is four instruc- tions in length so that simple service routines can be coded entirely in this space. Longer service routines require an addi- tional JUMP or CALL instruction. Individual interrupt requests are logically ANDed with the bits in the IMASK register; the highest-priority unmasked interrupt is then selected. The interrupt control register, ICNTL, allows the external interrupts to be set as either edge- or level-sensitive. Depending on Bit 4 in ICNTL, interrupt service routines can either be nested (with higher priority interrupts taking precedence) or be processed sequentially (with only one interrupt service active at a time). The interrupt force and clear register, IFC, is a write-only regis- ter that contains a force bit and a clear bit for each interrupt. When responding to an interrupt, the ASTAT, MSTAT and IMASK status registers are pushed onto the status stack and the PC counter is loaded with the appropriate vector address. The status stack is seven levels deep to allow interrupt nesting. The stack is automatically popped when a return from the inter- rupt instruction is executed. Pin Definitions Pin Function Descriptions show pin definitions for the ADSP- 216x processors. Any inputs not used must be tied to VDD. SYSTEM INTERFACE Figure 3 shows a typical system for the ADSP-216x with two serial I/O devices, an optional external program and data memory. A total of 12K words of data memory and 15K words of program memory is addressable. Programmable wait-state generation allows the processors to easily interface to slow external memories. The ADSP-216x processors also provide either: one external interrupt ( IRQ2) and two serial ports (SPORT0, SPORT1), or three external interrupts ( IRQ2, IRQ1, IRQ0) and one serial port (SPORT0). Clock Signals The ADSP-216x processors’ CLKIN input may be driven by a crystal or by a TTL-compatible external clock signal. The CLKIN input may not be halted or changed in frequency during operation, nor operated below the specified low frequency limit. If an external clock is used, it should be a TTL-compatible signal running at the instruction rate. The signal should be connected to the processor’s CLKIN input; in this case, the XTAL input must be left unconnected. Because the ADSP-216x processors include an on-chip oscilla- tor circuit, an external crystal may also be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 2. A parallel- resonant, fundamental frequency, microprocessor-grade crystal should be used. |
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