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ADSP-2163BP-100 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-2163BP-100 Datasheet(HTML) 10 Page - Analog Devices |
10 / 39 page REV. 0 ADSP-216x –10– Exiting Power-Down The power-down mode can be exited with the use of the PWDFLAG or RESET pin. Applying a low-to-high transition to the PWDFLAG pin takes the processor out of power-down mode. In this case, a delay of 4096 cycles is automatically in- duced by the processor. Also, depending on the status of the power-up context reset bit (pucr), the processor either 1) continues to execute instructions following the IDLE instruc- tion that caused the power-down. A RTI instruction is re- quired to pass control back to the main routine (pucr = 0) or 2) resumes operation from power-down by clearing the PC, STATUS, LOOP and CNTR stack. The IMASK and ASTAT registers are set to 0 and the SSTAT goes to 0x55. The processor then starts executing instructions from the address zero (pucr = 1). In the case where the power-down mode is exited by asserting the RESET pin, the processor state is reset and instruction are executed from address 0x0000. The RESET pin in this case must be held low long enough for the external crystal (if any) and the on-chip PLL to stabilize and lock. Low Power IDLE Instruction The IDLE instruction places the ADSP-216x processor in low power state in which it waits for an interrupt. When an interrupt occurs, it is serviced and execution continues with instruction following IDLE. Typically this next instruction will be a JUMP back to the IDLE instruction. This implements a low power standby loop. The IDLE n instruction is a special version of IDLE that slows the processor’s internal clock signal to further reduce power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor, n, given in the IDLE instruction. The syntax of the instruction is: IDLE n; where n = 16, 32, 64 or 128. The instruction leaves the chip in an idle state, operating at the slower rate. While it is in this state, the processor’s other inter- nal clock signals, such as SCLK, CLKOUT, and the timer clock, are reduced by the same ratio. Upon receipt of an en- abled interrupt, the processor will stay in the IDLE state for up to a maximum of n CLKIN cycles, where n is the divisor speci- fied in the instruction, before resuming normal operation. When the IDLE n instruction is used, it slows the processor’s internal clock and thus its response time to incoming interrupts– the 1-cycle response time of the standard IDLE state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-216x will remain in the IDLE state for up to a maxi- mum of n CLKIN cycles (where n = 16, 32, 64 or 128) before resuming normal operation. When the IDLE n instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the IDLE state (a maximum of n CLKIN cycles). ADSP-216x Prototyping You can prototype your ADSP-216x system with either ADSP- 2101 or ADSP-2103 RAM-based processors. When code is fully developed and debugged, it can be submitted to Analog Devices for conversion into an ADSP-216x ROM product. The ADSP-2101 EZ-ICE emulator can be used for development of ADSP-216x systems. For the 3.3 V ADSP-2162/ADSP-2164 and ADSP-2166, a voltage converter interface board provides 3.3 V emulation. Additional overlay memory is used for emulation of ADSP- 2161/ADSP-2162 systems. It should be noted that due to the use of off-chip overlay memory to emulate the ADSP-2161/ ADSP-2162, a performance loss may be experienced when both executing instructions and fetching program memory data from the off-chip overlay memory in the same cycle. This can be overcome by locating program memory data in on-chip memory. Ordering Procedure for ADSP-216x ROM Processors To place an order for a custom ROM-coded ADSP-2161, ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP- 2166 processor, you must: 1. Complete the following forms contained in the ADSP ROM Ordering Package, available from your Analog Devices sales representative: ADSP-216x ROM Specification Form ROM Release Agreement ROM NRE Agreement & Minimum Quantity Order (MQO) Acceptance Agreement for Preproduction ROM Products 2. Return the forms to Analog Devices along with two copies of the Memory Image File (.EXE file) of your ROM code. The files must be supplied on two 3.5" or 5.25" floppy disks for the IBM PC (DOS 2.01 or higher). 3. Place a purchase order with Analog Devices for nonrecurring engineering changes (NRE) associated with ROM product development. After this information is received, it is entered into Analog Devices’ ROM Manager System which assigns a custom ROM model number to the product. This model number will be branded on all prototype and production units manufactured to these specifications. To minimize the risk of code being altered during this process, Analog Devices verifies that the .EXE files on both floppy disks are identical, and recalculates the checksums for the .EXE file entered into the ROM Manager System. The checksum data, in the form of a ROM Memory Map, a hard copy of the .EXE file, and a ROM Data Verification form are returned to you for inspection. A signed ROM Verification Form and a purchase order for production units are required prior to any product being manu- factured. Prototype units may be applied toward the minimum order quantity. Upon completion of prototype manufacture, Analog Devices will ship prototype units and a delivery schedule update for production units. An invoice against your purchase order for the NRE charges is issued at this time. There is a charge for each ROM mask generated and a mini- mum order quantity. Consult your sales representative for de- tails. A separate order must be placed for parts of a specific package type, temperature range, and speed grade. |
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