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ECJ4YB1A106M Datasheet(PDF) 10 Page - Richtek Technology Corporation |
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ECJ4YB1A106M Datasheet(HTML) 10 Page - Richtek Technology Corporation |
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10 / 13 page  RT8055B 10 DS8055B-03 April 2011 www.richtek.com This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the Effective Series Resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎥⎦ ⎤ ⎢⎣ ⎡ + Δ ≤ Δ OUT L OUT 8fC 1 ESR I V Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8055B, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. OUT OUT L IN VV I = 1 fL V ⎡⎤ ⎡ ⎤ Δ× − ⎢⎥ ⎢ ⎥ × ⎣⎦ ⎣ ⎦ OUT OUT L(MAX) IN(MAX) VV L = 1 fI V ⎡⎤ ⎡ ⎤ ×− ⎢⎥ ⎢ ⎥ ×Δ ⎣⎦ ⎣ ⎦ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of ΔIL= 0.4(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : The inductor's current rating (caused a 40 °C temperature rising from 25 °C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : OUT IN RMS OUT(MAX) IN OUT V V II 1 VV =− |
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