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ADS4222 Datasheet(PDF) 10 Page - Texas Instruments |
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ADS4222 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 66 page O E O E O E O E O E E O E O E O E O E O N+1 N N+2 11 Clock Cycles (1) Input Clock CLKOUTM CLKOUTP Output Data (2) DxP, DxM DDR LVDS N-11 N-10 N-9 N-8 N-1 N N+1 N+2 11 Clock Cycles (1) CLKOUT Output Data D[13:0] Parallel CMOS Input Signal Sample N N+1 N+2 N+3 N+4 tPDI tA tPDI CLKM CLKP N-11 N-10 N-9 N-8 N+11 N+12 N+13 DAn_P DBn_P DAn_M DBn_M GND Logic0 V (1) ODL = 350mV - Logic1 V (1) ODH =+350mV V OCM ADS42B49 SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (1) With an external 100- Ω termination. Figure 1. LVDS Output Voltage Levels (1) The ADC latency after reset is 11 clock cycles. Overall latency = ADC latency + tPDI. (2) E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth). Figure 2. Latency Timing Diagram 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS42B49 |
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