ADC

CLOCK

DISTRIBUTION

MULTICHIP

SYNC

DC or

Fs/2

FIR FILTER

DC or

Fs/2

FIR FILTER

ADC

CONTROL

CLKOUT

GEN

SCLK

SDIO

SDO

SDENB

INA_P/N

INB_P/N

BUFFER

BUFFER

CLKOUT

GEN

PROGRAMMING

DATA

DACLKP/N

DBCLKP/N

DA[11:0]P/N

DB[11:0]P/N

CLKINP/N

SYNCP/N

SYNCOUTP/M

SYNCOUTP/N

VOLTAGE

REFERENCE

VREF

VCM

DEC

x2

BURST MODE

PROCESSING

DEC

x2

BURST MODE

PROCESSING

TRDYP/N

HRESP/N

BURST MODE

TRIGGER

OVERRANGE

THRESHOLD

INTERLEAVING

CORRECTION

Gain Correction

Offset Correction

Estimator

OVERRANGE

THRESHOLD

INTERLEAVING

CORRECTION

Gain Correction

Offset Correction

Estimator

ADS54T04

SLAS917 – DECEMBER 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DETAILED BLOCK DIAGRAM

Figure 1. Detailed Block Diagram

2

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