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DS90UB927Q Datasheet(PDF) 3 Page - Texas Instruments |
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DS90UB927Q Datasheet(HTML) 3 Page - Texas Instruments |
3 / 56 page 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 RxIN1- RxIN1+ RxIN2- RxIN2+ RxCLKIN- GPIO1 RxIN3- RxIN3+ GPIO0 RES1 CAPHS12 RES0 IDx CAPP12 DOUT- CMF VDD33_A PDB DOUT+ RxCLKIN+ DS90UB927Q TOP VIEW DAP = GND DS90UB927-Q1, DS90UB927Q, DS90UB927Q-Q1 www.ti.com SNLS416B – JUNE 2012 DS90UB927Q Pin Diagram Figure 2. DS90UB927Q — Top View Pin Descriptions Pin Name Pin # I/O, Type Description FPD-Link Input Interface RxIN[3:0]+ 38, 34, 32, 30 I, LVDS True LVDS Data Inputs Each pair requires external 100 Ω differential termination for standard LVDS levels RxIN[3:0]- 37, 33, 31, 29 I, LVDS Inverting LVDS Data Inputs Each pair requires external 100 Ω differential termination for standard LVDS levels RxCLKIN+ 36 I, LVDS True LVDS Clock Input The pair requires external 100 Ω differential termination for standard LVDS levels RxCLKIN- 35 I, LVDS Inverting LVDS Clock Input The pair requires external 100 Ω differential termination for standard LVDS levels LVCMOS Parallel Interface I2S_WC 1 I, LVCMOS Digital Audio Interface I2S Word Clock and I2S Bit Clock Inputs I2S_CLK 2 w/ pull down Shared with GPIO_REG7 and GPIO_REG8 Table 3 I2S_DA 3 I, LVCMOS Digital Audio Interface I2S Data Inputs I2S_DB 4 w/ pull down Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3 I2S_DC 5 I2S_DD 6 GPIO[1:0] 40, 39 I/O, LVCMOS General Purpose I/O w/ pull down See Table 1 REPEAT 21 I, LVCMOS Repeater Mode Select w/ pull down REPEAT = 0, Repeater Mode disabled (Default) REPEAT = 1, Repeater Mode enabled Requires a 10k Ω pull-up if set HIGH Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS90UB927-Q1 DS90UB927Q DS90UB927Q-Q1 |
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