Electronic Components Datasheet Search |
|
DAC8143FS Datasheet(PDF) 10 Page - Analog Devices |
|
DAC8143FS Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page DAC8143 –10– REV. C In many applications, the DAC8143’s zero scale error and low gain error, permit the elimination of external trimming compo- nents without adverse effects on circuit performance. For applications requiring a tighter gain error than 0.024% at 25 °C for the top grade part, or 0.048% for the lower grade part, the circuit in Figure 17 may be used. Gain error may be trimmed by adjusting R1. The DAC register must first be loaded with all 1s. R1 is then adjusted until VOUT = –VREF (4095/4096). In the case of an adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF adjusted to yield the desired full-scale output. BIPOLAR OPERATION (4-QUADRANT) Figure 18 details a suggested circuit for bipolar, or offset binary, operation. Table III shows the digital input-to-analog output relationship. The circuit uses offset binary coding. Twos comple- ment code can be converted to offset binary by software inver- sion of the MSB or by the addition of an external inverter to the MSB input. Resistor R3, R4 and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. Mismatching between R3 and R4 causes offset and full-scale error. Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be omitted by adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and adjusting either the amplitude of VREF or the value of R5 until the desired VOUT is achieved. Table III. Bipolar (Offset Binary) Code Table Digital Input Nominal Analog Output MSB LSB (VOUT as Shown in Figure 18) 1 1 1 1 1 1 1 1 1 1 1 1 +VREF 2047 2048 1 0 0 0 0 0 0 0 0 0 0 1 +VREF 1 2048 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 –VREF 1 2048 0 0 0 0 0 0 0 0 0 0 0 1 –VREF 2047 2048 0 0 0 0 0 0 0 0 0 0 0 0 –VREF 2048 2048 NOTES 1Nominal full scale for the circuits of Figure 18 is given by FS = VREF 2047 2048 . 2Nominal LSB magnitude for the circuits of Figure 18 is given by LSB = VREF 1 2048 . DAISY-CHAINING DAC8143s Many applications use multiple serial input DACs that use numerous interconnecting lines for address decoding and data lines. In addition, they use some type of buffering to reduce loading on the bus. The DAC8143 is ideal for just such an application. It not only reduces the number of interconnecting lines, but also reduces bus loading. The DAC8143 can be daisy- chained with only three lines: one data line, one CLK line and one load line, see Figure 19. VOUT 1/2 OP200 +5V R2 50 12 15 7 R1 100 SERIAL DATA INPUT VIN 14 15 1 2 3 6 13 4, 5 8-11 DGND VREF SRI CONTROL BITS SRO CONTROL INPUTS FROM SYSTEM RESET BUFFERED SERIAL DATA OUT VDD RFB AGND IOUT2 IOUT1 DAC8143 C1 10-33pF COMMON GROUND R3 10k A1 R4 20k R5 20k 1/2 OP200 A2 CLR Figure 18. Bipolar Operation (4-Quadrant, Offset Binary) |
Similar Part No. - DAC8143FS |
|
Similar Description - DAC8143FS |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |