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TPD5S115 Datasheet(PDF) 10 Page - Texas Instruments |
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TPD5S115 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 23 page  TPD5S115 SLVSBL2B – OCTOBER 2012 – REVISED MARCH 2013 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER PINS TEST CONDITIONS MIN TYP MAX UNIT Voltage Level Shifter- SCL, SDA Lines (x_A & x_B ports) VCCA = 1.2V A to B DDC channels enabled 394 ns TPHL Propagation delay B to A DDC channels enabled 347 ns A to B DDC channels enabled 504 ns TPLH Propagation delay B to A DDC channels enabled 171 ns TFALL A port fall time A-Port DDC channels enabled 146 ns TFALL B port fall time B-Port DCC channels enabled 135 ns TRISE A port rise time A-Port DCC channels enabled 190 ns TRISE B port rise time B-Port DCC channels enabled 93 ns FMAX Maximum switching frequency DCC channels enabled 400 kHz Voltage Level Shifter- CEC Line (x_A & x_B ports) VCCA = 1.2V A to B CEC channels enabled 550 ns TPHL Propagation delay B to A CEC channels enabled 350 ns A to B CEC channels enabled 13 µs TPLH Propagation delay B to A CEC channels enabled 290 ns TFALL A port fall time A-Port CEC channels enabled 146 ns TFALL B port fall time B-Port CEC channels enabled 200 ns TRISE A port rise time A-Port CEC channels enabled 190 ns TRISE B port rise time B-Port CEC channels enabled 16.4 µs Voltage Level Shifter- HPD Line (x_A & x_B ports) VCCA = 1.2V TPHL Propagation delay B to A CEC channels enabled 10.4 ns TPLH Propagation delay B to A CEC channels enabled 9.9 ns TFALL A port fall time A-Port CEC channels enabled 0.7 ns TRISE A port rise time A-Port CEC channels enabled 0.8 ns Voltage Level Shifter- SCL, SDA Lines (x_A & x_B ports) VCCA = 1.5V A to B DDC channels enabled 375 ns TPHL Propagation delay B to A DDC channels enabled 272 ns A to B DDC channels enabled 488 ns TPLH Propagation delay B to A DDC channels enabled 166 ns TFALL A port fall time A-Port DDC channels enabled 114 ns TFALL B port fall time B-Port DCC channels enabled 135 ns TRISE A port rise time A-Port DCC channels enabled 186 ns TRISE B port rise time B-Port DCC channels enabled 93 ns FMAX Maximum switching frequency DCC channels enabled 400 kHz Section 3.2B (Voltage Level Shifter- CEC Line (x_A & x_B ports) VCCA = 1.5V A to B CEC channels enabled 536 ns TPHL Propagation delay B to A CEC channels enabled 272 ns A to B CEC channels enabled 13 µs TPLH Propagation delay B to A CEC channels enabled 285 ns TFALL A port fall time A-Port CEC channels enabled 113 ns TFALL B port fall time B-Port CEC channels enabled 201 ns TRISE A port rise time A-Port CEC channels enabled 187 ns 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: TPD5S115 |
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