REV. PrK

EVAL-AD766XCB/AD767XCB

–4–

PRELIMINARY TECHNICAL DATA

Table III. EVAL-AD766XCB/AD767XCB Test Points

Test Point

Available Signal

TP1

DGND Digital ground

TP2

DGND Digital ground

TP3

SIG+

ADC Analog input

TP4

AGND Analog ground close to SIG+

TP5

R E F

ADC Reference input

TP6

BUSY

ADC BUSY signal

TP7

RD

ADC

RD signal

TP8

CS

ADC

CS signal

TP9

AGND Analog ground close to REF

TP10

CNVST ADC CNVST signal

TP11

MCLK divided by 2

TP12

OVDD ADC digital output supply

TP13

DVDD ADC digital core supply

TP14

VANA1 ADC analog supply

TP15

AGND Analog ground close to SIG-

TP16

S I G -

ADC Analog input

Table IV. Component values Vs. Input ranges ( AD7660 )

Input range

R1

R3

R6

R7

± 10V

8k

1k

8k

10k

± 5V

8k

2k

6.67k

10k

0 to -5V

8k

8k

0

none

Table V. Component values Vs. Input ranges ( AD7664 )

Input range

R1

R3

R6

R7

± 10V

2k

250

8k

10k

± 5V

2k

500

6.67k

10k

0 to -5V

1k

1k

0

none

Jumper

Default position

Function

Designation with the control

board ( Factory

settings)

TABLE II. JUMPER DESCRIPTION

JP13

A, U3 side

Selection of IMPULSE. When the button of the switch is close to J4 connector

( not A position ), the ADC uses the IMPULSE mode which is the mode with the

lowest power dissipation. With the AD7660, JP13 is a spare switch.

JP14

A, U3 side

TEST1. For factory use only and it is pull down.

JP15

A, U3 side

TEST0. For factory use only and it is pull down.

JP16

A, U3 side

Selection of EXT/

INT ( use of external or internal serial clock ). When the button of

the switch is close to J4 connector ( not A position ) and when the serial reading

mode is selected, the data are read with an external serial clock SCLK generated from

the master clock MCLK otherwise the data are read with the ADC serial clock. When

external serial clock reading mode is selected, MCLK has to be fast enough to be able

the read the data properly as explained in the AD766X data sheet. JP16 has no use in

parallel reading mode.

JP17

A, U3 side

Selection of INVSYNC ( SYNC active level ). When the button of the switch is close

to J4 connector ( not A position ) and when the master serial reading mode is se

lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or

slave serial reading mode.

JP18

A, U3 side

Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close

to J4 connector ( not A position ) and when the serial reading mode is selected,

INVSCLK is high. JP18 has no use in parallel reading mode.

JP19

not A

Selection of

CNVST signal. When JP19 is in position A, the signal on J3 is used

otherwise the on-board

CNVST generation is used. MCLK signal is used to generate

the on-board

CNVST signal.

JP20

not A

Selection of REF signal. When JP20 is in position A, the REF is buffered. When

JP20 is not in position A, the REF is not buffered.