Electronic Components Datasheet Search |
|
BQ34Z653DBT Datasheet(PDF) 2 Page - Texas Instruments |
|
|
BQ34Z653DBT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 25 page bq34z653 SLUSB53 –JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. AVAILABLE OPTIONS PACKAGE(1) TA 44-PIN TSSOP (DBT) Tube 44-PIN TSSOP (DBT) Tape and Reel –40°C to 85°C bq34z653DBT(2) bq34z653DBTR(3) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) A single tube quantity is 40 units. (3) A single reel quantity is 2000 units. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. THERMAL INFORMATION bq34z653 THERMAL METRIC(1) TSSOP UNITS 44 PINS θJA, High K Junction-to-ambient thermal resistance(2) 60.9 θJC(top) Junction-to-case(top) thermal resistance (3) 15.3 θJB Junction-to-board thermal resistance (4) 30.2 °C/W ψJT Junction-to-top characterization parameter (5) 0.3 ψJB Junction-to-board characterization parameter (6) 27.2 θJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): bq34z653 |
Similar Part No. - BQ34Z653DBT |
|
Similar Description - BQ34Z653DBT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |