1

2

3

4

5

10

9

8

7

6

IN

ISET

VSS

PRETERM

PG

NC

ISET2

CHG

TS

OUT

bq2409x

bq24090, bq24091

bq24092, bq24093

bq24095

www.ti.com

SLUS968D – JANUARY 2010 – REVISED DECEMBER 2012

PIN CONFIGURATION

PIN FUNCTIONS

NAME

PIN

I/O

DESCRIPTION

Input power, connected to external DC supply (AC adapter or USB port). Expected range of bypass

IN

1

I

capacitors 1

Battery Connection. System Load may be connected. Average load should not be excessive, allowing

OUT

10

O

battery to charge within the 10 hour safety timer window. Expected range of bypass capacitors 1

μF to

10

μF.

Programs the Current Termination Threshold (5 to 50% of Iout which is set by ISET) and Sets the Pre-

PRE-TERM

4

I

Charge Current to twice the Termination Current Level.

Expected range of programming resistor is 1k to 10k

Ω (2k: Ipgm/10 for term; Ipgm/5 for precharge)

Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast charge current

ISET

2

I

value. Range is 10.8k (50mA) to 540

Ω (1000mA).

Programming the Input/Output Current Limit for the USB or Adaptor source:

ISET2

7

I

High = 500mAmax, Low = ISET, FLOAT = 100mA max.

Temperature sense pin connected to bq24090/2/5 -10k at 25°C NTC thermistor & bq24091/3 -100k at

25°C NTC thermistor, in the battery pack. Floating TS Pin or pulling High puts part in TTDM “Charger”

TS

9

I

Mode and disable TS monitoring, Timers and Termination. Pulling pin Low disables the IC. If NTC

sensing is not needed, connect this pin to VSS through an external 10 k

Ω/100kΩ resistor. A 250kΩ from

TS to ground will prevent IC entering TTDM mode when battery with thermistor is removed.

VSS

3

–

Ground terminal

CHG

8

O

Low (FET on) indicates charging and Open Drain (FET off) indicates no Charging or Charge complete.

PG

5

O

Low (FET on) indicates the input voltage is above UVLO and the OUT (battery) voltage.

NC

6

NA

Do not make a connection to this pin (for internal use) – Do not route through this pin

There is an internal electrical connection between the exposed thermal pad and the VSS pin of the

Thermal PAD

Pad

device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit

–

and Package

board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be

connected to ground at all times

Copyright © 2010–2012, Texas Instruments Incorporated

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Product Folder Links: bq24090 bq24091 bq24092 bq24093 bq24095