VDD

IDAC_OUT

GND

VIDS

VIDC

VIDB

VIDA

SET

1

3

2

5

4

10

9

8

7

6

DAP

EN

MODE

LM10011

SNVS822 – DECEMBER 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAM

SON-10 3mm x 3mm

0.5mm pitch

TOP VIEW

PIN DESCRIPTIONS

PIN

DESCRIPTION

NAME

NO.

GND

1

Ground.

IDAC_OUT

2

Output pin of the current DAC that connects to the feedback node of the regulator.

Positive supply input. Operating voltage is 2.97V to 5.5V. It is recommended to add a small 1nF or greater

VDD

3

bypass capacitor from this pin to GND.

EN

4

Precision enable input. The LM10011 will operate when the EN pin voltage exceeds 1.34V.

MODE will set the VID operating mode. Connecting MODE to VDD will select a 4-bit parallel interface.

MODE

5

Connecting MODE to GND will select a 4 pin, 6-bit interface.

A resistor connected from SET to GND will set the start-up code (current) at the IDAC_OUT pin. There are

SET

6

16 different start-up codes to select from.

VID digital input. In 6-bit mode: Bit 0 when VIDS transitions low; Bit 3 when VIDS transitions high. In 4-bit

VIDA

7

mode: Bit 0.

VID digital input. In 6-bit mode: Bit 1 when VIDS transitions low; Bit 4 when VIDS transitions high. In 4-bit

VIDB

8

mode: Bit 1.

VID digital input. In 6-bit mode: Bit 2 when VIDS transitions low; Bit 5 when VIDS transitions high. In 4-bit

VIDC

9

mode: Bit 2.

VID select line. In 6-bit mode: Transition low selects lower 3 bits, Transition high selects upper 3 bits and

VIDS

10

updates the IDAC_OUT current to reflect the present VID code. In 4-bit mode: Bit 3.

Die Attach Pad. Not electrically connected to device, connect to system ground plane for reduced thermal

DAP

DAP

resistance.

2

Copyright © 2012, Texas Instruments Incorporated

Product Folder Links: LM10011