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F28M36P53C2ZWTQ Datasheet(PDF) 1 Page - Texas Instruments |
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F28M36P53C2ZWTQ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 202 page  F28M36P63B2, F28M36P63C2 F28M36P53B2, F28M36P53C2, F28M36P33B2, F28M36P33C2 www.ti.com SPRS825 – OCTOBER 2012 Concerto Microcontrollers 1 F28M36x (Concerto™) MCUs 1.1 Features 12 • Master Subsystem — ARM® Cortex™-M3 • Control Subsystem — TMS320C28x™ 32-Bit CPU – 125 MHz – 150 MHz – Cortex™-M3 Core Hardware Logic Built-in Self Test – C28x Core Hardware Logic Built-in Self Test – Embedded Memory – Embedded Memory • Up to 1MB Flash (ECC) • Up to 512KB Flash (ECC) • Up to 128KB RAM (ECC or Parity) • Up to 36KB RAM (ECC or Parity) • Up to 64KB Shared RAM • Up to 64KB Shared RAM • 2KB IPC Message RAM • 2KB IPC Message RAM – 5 Universal Asynchronous – IEEE-754 Single-Precision Floating-Point Receiver/Transmitters (UARTs) Unit (FPU) – 4 Synchronous Serial Interfaces (SSIs)/ – Viterbi, Complex Math, CRC Unit (VCU) Serial Peripheral Interface (SPI) – Serial Communications Interface (SCI) – 2 Inter-integrated Circuits (I2Cs) – Serial Peripheral Interface (SPI) – Universal Serial Bus On-the-Go (USB-OTG) + – Inter-Integrated Circuit (I2C) PHY – 6-Channel Direct Memory Access (DMA) – 10/100 ENET 1588 MII – 12 Enhanced Pulse Width Modulator (ePWM) – 2 Controller Area Networks (CANs) Modules – 32-Channel Direct Memory Access (µDMA) • 24 Outputs (16 High-Resolution) – Dual Security Zones (128-Bit Password per – 6 32-Bit Enhanced Capture (eCAP) Modules Zone) – 3 32-Bit Enhanced Quadrature Encoder – External Peripheral Interface (EPI) (eQEP) Modules – Micro Cyclic Redundancy Check (µCRC) – Multichannel Buffered Serial Port (McBSP) Module – External Peripheral Interface (EPI) – 4 General-Purpose Timers – One Security Zone (128-Bit Password) – 2 Watchdog Timer Modules – 3 32-Bit Timers – Endianness: Little Endian – Endianness: Little Endian • Clocking – On-chip Crystal Oscillator/External Clock • Analog Subsystem Input – Dual 12-Bit Analog-to-Digital Converters – Dynamic PLL Ratio Changes Supported (ADCs) • 1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design – Up to 2.88 MSPS – Up to 24 Channels • Interprocessor Communications (IPC) – 4 Sample-and-Hold (S/H) Circuits – 32 Handshaking Channels – Up to 6 Comparators With 10-Bit Digital-to- – 4 Channels Generate IPC Interrupts Analog Converter (DAC) – Can be Used to Coordinate Transfer of Data Through IPC Message RAMs • Package – 289-Ball ZWT Plastic Ball Grid Array (PBGA) • Up to 142 Individually Programmable, Multiplexed GPIO Pins – Glitch-free I/Os 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of Copyright © 2012, Texas Instruments Incorporated development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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