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TPS25910 Datasheet(PDF) 7 Page - Texas Instruments |
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TPS25910 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 25 page OUT IN OUT V V 0.04 I = - ´ LIM 1.02912 LIM 205.62 R I = LIM 0.976944 LIM 197.388 R I = ( ) OUT CHARGE EXT INT dV I C C dt = + TPS25910 www.ti.com SLUSAR6B – SEPTEMBER 2012 – REVISED MARCH 2013 PIN DESCRIPTION FLT: Open-drain output that pulls low during thermal shutdown. FLT activates when device thermally shuts down and deactivates when die temperature cools down below the device thermal protection threshold and the device ends thermal shutdown cycle. FLT becomes operational before UV, when VIN is greater than 1V. GND: This is the most negative voltage in the circuit and is used as reference for all voltage measurements unless otherwise specified. All the GND pins must be connected to system power supply negative return point GATE: Output that provides gate drive for the internal pass FET. Its sourcing current is about 11 µA. An internal clamp prevents GATE from rising 6.6 V above OUT. CINT is 200 pF. The GATE pin is disabled by the following mechanisms: 1. When EN is above its rising threshold, GATE is pulled down by a 40- Ω resistor connecting to GND for approximately 50 µs. Then, a 7.5-k Ω resistor ties GATE to GND to ensure the GATE is off. 2. When VIN drops below the UVLO threshold, GATE is pulled down by a 40-Ω resistor connecting to GND for approximately 50 µs. Then, a 7.5-k Ω resistor ties GATE to GND to ensure the GATE is off. 3. When short circuit fault occurs, GATE is pulled down by a 40- Ω resistor connecting to GND for approximately 50 µs. Then, a 500 µA current source continues to pull down on the GATE. 4. If the chip die temperature exceeds the OTSD rising threshold, GATE is pulled down to GND by a 7.5-k Ω resistor. An external capacitor can be connected from GATE pin to GND pin to create linear inrush profile. The slew rate of the inrush can be controlled by a different capacitor value. (1) Where: ICHARGE is 11 µA (typical) CINT, the equivalent gate input capacitance of the internal FET (200 pF typical). . ILIM: A resistor connected from this pin to ground sets I(LIM). RLIM is set by the formula: for currents below 2 A where RLIM is in kΩ. (2) for currents above 2 A where RLIM is in kΩ. (3) EN: When this pin is pulled low, the device is enabled. The input threshold is hysteretic, allowing the user to program a startup delay with an external RC circuit. EN is pulled to VIN by a 10-M Ω resistor, pulled to GND by 16.8 M Ω and is clamped to ground by a 7-V Zener diode. Because high impedance pullup and or down resistors are used to reduce current draw, any external FET controlling this pin should be low leakage. IN: Input voltage to the TPS25910. The recommended operating voltage range is 3 V to 20 V. All VIN pins should be connected together and to the power source. OUT: Output connection for the TPS25910. When switched on, the output voltage is approximately: (4) All OUT pins should be connected together and to the load. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS25910 |
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