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UCC27528DR Datasheet(PDF) 3 Page - Texas Instruments |
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UCC27528DR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 31 page UCC27527 UCC27528 www.ti.com SLUSBD0B – DECEMBER 2012 – REVISED JANUARY 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT Supply voltage range, VDD 4.5 12 18 V Operating junction temperature range -40 140 °C Input voltage, INA, INB, INA+, INA-, INB+, INB- -5 18 V Enable voltage, ENA and ENB 0 18 THERMAL INFORMATION UCC27527, UCC27528 THERMAL METRIC D DSD UNITS 8 PINS 8 PINS θJA Junction-to-ambient thermal resistance(1) 128 46.1 θJCtop Junction-to-case (top) thermal resistance(2) 77.7 50.7 θJB Junction-to-board thermal resistance(3) 68.5 21.8 °C/W ψJT Junction-to-top characterization parameter(4) 20.7 1.1 ψJB Junction-to-board characterization parameter(5) 68.0 22.0 θJCbot Junction-to-case (bottom) thermal resistance(6) n/a 9.0 (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: UCC27527 UCC27528 |
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