UCD74111

SLUSAT8 – OCTOBER 2012

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Synchronous Rectifier Enable Input (SRE)

The SRE (synchronous rectifier enable) pin is a digital input with an internal ,10-k

Ω, pull-up resistor connected to

the 3.3-V input. It is designed to accept 3.3-V logic levels, but is also tolerant of 5-V levels. The SRE mode pin

sets the behavior of the SRE pin. When the SRE mode pin is asserted high, the device enters synchronous

mode. In synchronous mode, the input, when asserted high, enables the operation of the low-side synchronous

rectifier FET. The PWM input controls the state of the low-side gate drive signal . When SRE is asserted low

while in synchronous mode, the low-side FET gate drive holds low, keeping the FET off. While remaining OFF,

the low-side FET restricts the current flow to the intrinsic body diode. When the SRE mode pin is asserted low,

the device enters independent mode. In independent mode, the state of the low-side gate drive signal follows the

state of the SRE signal. It is completely independent of the state of the PWM signal. No anti-cross-conduction

logic is active in independent mode. The user must ensure that the PWM and SRE signals do not overlap.

The logic threshold of this pin typically exhibits 450 mV of hysteresis to provide noise immunity and ensure glitch-

free operation of the low-side gate driver.

SRE Mode (SRE_MD)

The SRE mode pin is a digital input that accept 3.3-V logic levels, and levels up to 5-V. The SRE pin sets the

operational mode on the device. When asserted high, the device enters synchronous mode. In synchronous

mode, the PWM input controls the behavior of both the high-side and low-side gate drive signals. When asserted

low, this pin configures the device for independent mode. In independent mode the PWM pin controls the high-

side FET and the SRE pin controls the low-side FET. The SRE mode pin should be s permanently tied high or

low depending on the power architecture being implemented. It not intended to be switched dynamically while the

device is in operation. This pin can be tied to the BP3 pin to always select synchronous mode.

Input Voltage for Internal Circuits (VDD)

The VDD pin supplies power to the internal circuits of the device. An internal linear regulator that provides the

produces an internal 3.3-V supply that powers the internal analog and digital functional blocks. The BP3 pin

provides access for a high frequency bypass capacitor on this internal rail. The VGG regulator produces a

nominal output of 6.4 V. The undervoltage lockout (UVLO) circuitry monitors the output of the VGG regulator.

The device does not attempt to produce gate drive pulses until the VGG voltage is above the UVLO threshold.

This delay ensures that there is sufficient voltage available to drive the power FETs into saturation when

switching activity begins.

Voltage Supply for Gate Drive and Internal Control Circuitry (VGG and AVGG)

The VGG pin is the gate drive voltage for the high current gate drive stages. The AVGG pin is the voltage supply

to internal control circuitry. The on-chip regulator can supply the voltage internally on the VGG pin, or the user

can supply the voltage externally.. When using the internal regulator, the VGG_DIS pin should be tied low. When

an external source of VGG is to be used, the VGG_DIS pin must be tied high. Current is drawn from the VGG

supply in fast, high-current pulses. Connect s 4.7-µF ceramic capacitor between the VGG pin and PGND pin as

close as possible to the package.

Connect a resistor with a value between 1

Ω and 2 Ω between the AVGG pin and the VGG pin. A low ESR

bypass ceramic capacitor of 100 nF or greater needs to be connected from AVGG pin to AGND as well.

Whether the voltage is internally or externally supplied, UVLO circuitry monitors the voltage on the VGG pin. The

voltage must be higher than the UVLO threshold before power conversion can occur. Note that the FLT pin is

VGG Disable (VGG_DIS)

The VGG_DIS pin, when asserted high, disables the on-chip VGG linear regulator. When tied low, the VGG

the power architecture being implemented. The VGG_DIS pin should not be switched dynamically while the

device is in operation.

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