MMBF4391LT1 datasheet(3/6 Pages) MOTOROLA | JFET Switching Transistors

3 page

MMBF4391LT1 MMBF4392LT1 MMBF4393LT1

Motorola Small–Signal Transistors, FETs and Diodes Device Data

Figure 5. Switching Time Test Circuit

Figure 6. Typical Forward Transfer Admittance

Figure 7. Typical Capacitance

ID, DRAIN CURRENT (mA)

2.0

5.0

3.0

7.0

0.5

1.0

3.0

7.0

5.0

0.7

2.0

3.0

5.0

7.0

0.5

1.0

3.0

5.0

0.3

0.1

0.05

0.03

VR, REVERSE VOLTAGE (VOLTS)

Tchannel = 25°C

VDS = 15 V

Tchannel = 25°C

(Cds is negligible

Cgs

–VDD

VGG

RGG

RGEN

Ω

VGEN

OUTPUT

INPUT

Ω

SET VDS(off) = –10 V

INPUT PULSE

tr ≤ 0.25 ns

tf ≤ 0.5 ns

PULSE WIDTH = 2.0

µs

DUTY CYCLE

≤ 2.0%

RGG > RK

RD’ = RD(RT + 50)

RD + RT + 50

Figure 8. Effect of Gate–Source Voltage

on Drain–Source Resistance

120

160

200

1.0

3.0

170

5.0

–10

–40

2.0

140

–70

VGS, GATE–SOURCE VOLTAGE (VOLTS)

4.0

100 mA

125 mA

75 mA

50 mA

25 mA

IDSS

= 10

Tchannel = 25°C

Figure 9. Effect of Temperature on Drain–Source

On–State Resistance

1.8

1.0

2.0

1.2

1.4

1.6

0.8

0.6

0.4

ID = 1.0 mA

VGS = 0

Tchannel, CHANNEL TEMPERATURE (°C)

1.5

1.0

Cgd

110

6.0

7.0

8.0

MMBF4393

MMBF4392

MMBF4391

NOTE 1

The switching characteristics shown above were measured using a test

circuit similar to Figure 5. At the beginning of the switching interval, the

gate voltage is at Gate Supply Voltage (–VGG). The Drain–Source Voltage

(VDS) is slightly lower than Drain Supply Voltage (VDD) due to the voltage

divider. Thus Reverse Transfer Capacitance (Crss) of Gate–Drain Capaci-

tance (Cgd) is charged to VGG + VDS.

During the turn–on interval, Gate–Source Capacitance (Cgs) discharges

through the series combination of RGen and RK. Cgd must discharge to

VDS(on) through RG and RK in series with the parallel combination of effec-

tive load impedance (R’D) and Drain–Source Resistance (rDS). During the

turn–off, this charge flow is reversed.

Predicting turn–on time is somewhat difficult as the channel resistance

rDS is a function of the gate–source voltage. While Cgs discharges, VGS

approaches zero and rDS decreases. Since Cgd discharges through rDS,

turn–on time is non–linear. During turn–off, the situation is reversed with

rDS increasing as Cgd charges.

The above switching curves show two impedance conditions; 1) RK is

equal to RD’ which simulates the switching behavior of cascaded stages

where the driving source impedance is normally the load impedance of the

previous stage, and 2) RK = 0 (low impedance) the driving source imped-

ance is that of the generator.

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