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LTC3388-1 Datasheet(PDF) 5 Page - Linear Technology |
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LTC3388-1 Datasheet(HTML) 5 Page - Linear Technology |
5 / 20 page LTC3330 5 3330p For more information www.linear.com/LTC3330 elecTrical characTerisTics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ILEAK(P) PMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA ILEAK(N) NMOS Switch Leakage Buck/Buck-Boost Regulators –20 20 nA Maximum Buck Duty Cycle Buck/Buck-Boost Regulators l 100 % PGVOUT Threshold As a Percentage of VOUT Target l 90 92.5 95 % PGLDO Threshold As a Percentage of LDO_OUT Target l 90 92.5 95 % VIH Digital Input High Voltage Pins LDO_EN, OUT[2:0], LDO[2:0], IPK[2:0], UV[3:0] l 1.2 V VIL Digital Input Low Voltage Pins LDO_EN, OUT[2:0], LDO[2:0], IPK[2:0], UV[3:0] l 0.4 V IIH Digital Input High Current Pins LDO_EN, OUT[2:0], LDO[2:0], IPK[2:0], UV[3:0] 0 10 nA IIL Digital Input Low Current Pins LDO_EN, OUT[2:0], LDO[2:0], IPK[2:0], UV[3:0] 0 10 nA VOH PGVOUT, PGLDO, EH_ON Output High Voltage VIN3 = 5V, 10µA Out of Pin l 4.6 V VOL PGVOUT, PGLDO, EH_ON Output Low Voltage VIN3 = 5V, 10µA into Pin l 0.4 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3330E is tested under pulsed load conditions such that TJ ≈ TA. The LTC3330E is guaranteed to meet specifications from 0°C to 85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA). Note 4: Dynamic supply current is higher due to gate charge being delivered at the switching frequency. |
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Similar Description - LTC3388-1 |
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